Patents Examined by Abul Kalam
  • Patent number: 10748787
    Abstract: A semiconductor device includes an insulating carrier structure comprised of an insulating inorganic material. The carrier structure has a receptacle in which a semiconductor chip is disposed. The semiconductor chip has a first side, a second side and a lateral rim. The carrier structure laterally surrounds the semiconductor chip and the lateral rim. The semiconductor device also includes a metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 18, 2020
    Assignee: Infineon Technologies AG
    Inventors: Carsten von Koblinski, Ulrike Fastner, Andre Brockmeier, Peter Zorn
  • Patent number: 10727370
    Abstract: Provided is an optical device including an active layer, which includes two outer barriers and a coupled quantum well between the two outer barriers. The coupled quantum well includes a first quantum well layer, a second quantum well layer, a third quantum well layer, a first coupling barrier between the first quantum well layer and the second quantum well layer, and a second coupling barrier between the second quantum well layer and the third quantum well layer. The second quantum well layer is between the first quantum well layer and the third quantum well layer. An energy band gap of the second quantum well layer is less than an energy band gap of the first quantum well layer, and an energy band gap of the third quantum well layer is equal to or less than the energy band gap of the second quantum well layer.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byunghoon Na, Changyoung Park, Yonghwa Park
  • Patent number: 10714531
    Abstract: Focal plane arrays and infrared detector device having a transparent common ground structure and methods of their fabrication are disclosed. In one embodiment, a front-side illuminated infrared detector device includes a contact layer and a detector structure adjacent to the contact layer. The detector structure is capable of absorbing radiation. The front-side illuminated infrared detector device further includes a common ground structure adjacent the detector structure, wherein the common ground structure is transmissive to radiation having a wavelength in a predetermined spectral band, and the common ground structure has a bandgap that is wider than a bandgap of the detector structure. The front-side illuminated infrared detector device further includes an optical layer adjacent the common ground structure.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: July 14, 2020
    Assignee: L3 Cincinnati Electronics Corporation
    Inventors: Yajun Wei, Steven Allen, Michael Garter, Mark Greiner, David Forrai, Darrel Endres
  • Patent number: 10707314
    Abstract: A stack including doped semiconductor strips, a one-dimensional array of gate electrode strips, and a dielectric matrix layer is formed over a substrate. A two-dimensional array of openings is formed through the dielectric matrix layer and the one-dimensional array of gate electrode strips. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of openings. Each of the tubular gate electrode portions is formed directly on a respective one of the gate electrode strips. Gate dielectrics are formed on inner sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surrounding gate electrodes is formed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 7, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Seje Takaki, Jongsun Sel, Hisakazu Otoi, Chao Feng Yeh
  • Patent number: 10685889
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate including a core region and a peripheral region, forming a plurality of first fin structures in the peripheral region and a plurality of second fin structures in the core region, forming a first dummy gate structure including a first dummy oxide layer and a first dummy gate electrode layer on each first fin structure, and forming a second dummy gate structure including a second dummy oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate structure and then forming a first gate oxide layer on the exposed portion of each first fin structure, and removing each second dummy gate structure. Finally, the method includes forming a first gate structure on each first fin structure and a second gate structure on each second fin structure.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10684499
    Abstract: A splicing screen includes: at least two display panels spliced together, each display panel having a display surface; a curved area bending towards a back side of the display surface at a splicing area; and a substantially flat area; a transparent cover disposed at a side of the display surface and covering at least the curved area of each display panel; and a plurality of support portions between the transparent cover and the curved area of each of the display panels and forming a plurality of meshes extending from the display panel to the transparent cover, an inner wall of each mesh having a reflective surface.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 16, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Mingchao Wang, Junwei Wang, Dongxi Li
  • Patent number: 10665724
    Abstract: A method and apparatus wherein the method comprises: providing at least one electrode within a semiconductor layer wherein the semiconductor layer is provided on a first side of a wafer; thinning the wafer to produce a thinned wafer; providing graphene on a second side of the thinned wafer; attaching the semiconductor layer to an electrical interface on the first side of the thinned wafer; and providing at least one electrical connection from the graphene to the electrical interface so as to form a transistor comprising the at least one electrode and the graphene.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 26, 2020
    Assignee: LytEn, Inc.
    Inventors: Katri Pohjonen, Sami Kallioinen, Markku Rouvala
  • Patent number: 10658403
    Abstract: A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield can be increased to effectively improve productivity. Heavy and light ion doping can be simultaneously achieved with one single doping operation so that manufacturing cost can be reduced. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to contact the two ends of the active layer thereby effectively reducing contact resistance and improving product yield. Also provided is a TFT substrate manufactured with the method.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: May 19, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuanfu Liu
  • Patent number: 10651429
    Abstract: An organic light-emitting diode (OLED) illuminating lamp sheet and a manufacturing method thereof are provided. The method for manufacturing an OLED illuminating lamp sheet includes: manufacturing an array substrate, the array substrate includes a first base and a first electrode formed on the first base; bonding an electrostatic film to a surface of the array substrate provided with the first electrode, forming a patterned electrostatic film by patterning the electrostatic film, and forming an organic film layer by taking the patterned electrostatic film as a mask; forming a second electrode and obtaining an OLED element; and encapsulating the OLED element and obtaining an OLED illuminating lamp sheet.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: May 12, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jie Sun, Chung Chun Lee, Chieh Hsing Chung
  • Patent number: 10643862
    Abstract: The present invention discloses a system-level packaging method and packaging system based on 3D printing.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 5, 2020
    Assignee: INSTITUTE OF GEOLOGY AND GEOPHYSICS CHINESE ACADEMY OF SCIENCES
    Inventors: Zongwei Li, Xingyin Xiong, Kedu Han, Changchun Yang
  • Patent number: 10644032
    Abstract: The present invention discloses a flexible display substrate including a first flexible substrate and a plurality of display elements disposed on a first side of the first flexible substrate, each of the display elements including a thin film transistor. The flexible display substrate further includes a plurality of protrusions each provided on a second side of the first flexible substrate opposite to the first side and corresponding to a respective thin film transistor in a thickness direction of the first flexible substrate. A projection area of each protrusion, in the thickness direction of the first flexible substrate, on the second side of the first flexible substrate at least partially overlaps with a projection area of the thin film transistor corresponding to the protrusion, in the thickness direction of the first flexible substrate, on the second side of the first flexible substrate.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: May 5, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongfei Cheng, Yuxin Zhang
  • Patent number: 10643915
    Abstract: A lead bonding structure includes: a plurality of leads extending outward from a package; and a plurality of electrode pads formed on a circuit board. The plurality of leads are soldered to the electrode pads, respectively. Each of the leads includes a lower wide portion having a width dimension greater than a width dimension of each of the electrode pads. The lower wide portion of each of the leads is soldered to the corresponding electrode pad.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: May 5, 2020
    Assignee: Japan Aviation Electronics Industry, Ltd.
    Inventors: Hiroshi Akimoto, Takushi Yoshida
  • Patent number: 10629702
    Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Thamarai S. Devarajan, Balasubramanian Pranatharthiharan, Sanjay C. Mehta, Muthumanickam Sankarapandian
  • Patent number: 10609489
    Abstract: A diaphragm and suspension for an electroacoustic transducer are formed by depositing a layer of compliant material on a first surface of a solid substrate and removing material from a second surface of the solid substrate. The removal leaves a block of substrate material suspended within an inner perimeter of an outer support ring of the substrate material by the compliant material, the block providing the diaphragm.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: March 31, 2020
    Assignee: Bose Corporation
    Inventors: Csaba Guthy, Ole Mattis Nielsen, Mark A. Hayner
  • Patent number: 10600638
    Abstract: A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John Zhang
  • Patent number: 10573511
    Abstract: The present invention relates to methods of forming silicon nitride thin films on a substrate in a reaction chamber by plasma enhanced atomic layer deposition (PEALD). Exemplary methods include the steps of (i) introducing an octahalotrisilane Si3X8 silicon precursor, such as octachlorotrisilane (OCTS) Si3Cl8, into a reaction space containing a substrate, (ii) introducing a nitrogen containing plasma into the reaction space, and wherein steps (i), (ii) and any steps in between constitute one cycle, and repeating said cycles a plurality of times until an atomic layer nitride film having a desired thickness is obtained.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 25, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Antti Niskanen, Suvi Haukka, Jaakko Anttila
  • Patent number: 10573568
    Abstract: A method of producing a semiconductor component is provided. The method includes providing a silicon substrate having a <111>-surface defining a vertical direction, forming in the silicon substrate at least one electronic component, forming at least two epitaxial semiconductor layers on the silicon substrate to form a heterojunction above the <111>-surface, and forming a HEMT-structure above the <111>-surface.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: February 25, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Gebhart Dippold
  • Patent number: 10559719
    Abstract: Solid-state radiation transducer (SSRT) devices having buried contacts that are at least partially transparent and associated systems and methods are disclosed herein. An SSRT device configured in accordance with a particular embodiment can include a radiation transducer including a first semiconductor material, a second semiconductor material, and an active region between the first semiconductor material and the second semiconductor material. The SSRT device can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. The second contact can include a plurality of buried-contact elements electrically coupled to the second semiconductor material. Individual buried-contact elements can have a transparent portion directly adjacent to the second semiconductor material. The second contact can further include a base portion extending between the buried-contact elements, such as a base portion that is least partially planar and reflective.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: February 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov, Lifang Xu
  • Patent number: 10558181
    Abstract: When controlling values of a plurality of parameters in a predetermined device according to an operation by a user, values of parameters to be controlled are displayed in an array along an item axis on a parameter editing screen, an operation by the user to the parameter editing screen is detected, and when an operation to trace the screen in a direction of the item axis from a certain position is detected, a sequential control is performed, sequentially according to progress of the operation, to temporarily change to a specific value a value of each parameter corresponding to a position in the item axis direction where the trace operation is being performed.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: February 11, 2020
    Assignee: YAMAHA CORPORATION
    Inventor: Kotaro Terada
  • Patent number: 10559721
    Abstract: A light emitting device includes a substrate, a light emitting element, a light reflecting resin member, a sealing member, an electrically conductive wiring and a lens member. The light reflecting resin member surrounds the light emitting element. The sealing member is disposed in a region surrounded by the light reflecting resin member. The electrically conductive wiring is arranged on an upper surface of the substrate such that the substrate includes an exposed region exposed from the electrically conductive wiring with at least a part of the exposed region of the substrate being embedded in the light reflecting resin member. The lens member is disposed above the light emitting element to reach an outer edge of the substrate. The lens member is in contact with an upper surface of the sealing member and an upper surface and an outer lateral surface of the light reflecting resin member.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: February 11, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Motokazu Yamada, Mototaka Inobe