Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

Abstract: A method for fabricating a semiconductor structure includes providing a base structure including a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in a first transistor region, and a plurality of second openings formed in the dielectric layer in a second transistor region. The method also includes forming a first work function layer an the dielectric layer covering bottom and sidewall surfaces of the first and the second openings, forming a first sacrificial layer in each first opening and each second opening with a top surface lower than the top surface of the dielectric layer, removing a portion of the first work function layer exposed by the first sacrificial layer, removing the first work function layer formed in each first opening, and forming a second work function layer and a gate electrode in each first opening and each second opening.

Abstract: A semiconductor device includes an insulating carrier structure comprised of an insulating inorganic material. The carrier structure has a receptacle in which a semiconductor chip is disposed. The semiconductor chip has a first side, a second side and a lateral rim. The carrier structure laterally surrounds the semiconductor chip and the lateral rim. The semiconductor device also includes a metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure.

Abstract: Provided is an optical device including an active layer, which includes two outer barriers and a coupled quantum well between the two outer barriers. The coupled quantum well includes a first quantum well layer, a second quantum well layer, a third quantum well layer, a first coupling barrier between the first quantum well layer and the second quantum well layer, and a second coupling barrier between the second quantum well layer and the third quantum well layer. The second quantum well layer is between the first quantum well layer and the third quantum well layer. An energy band gap of the second quantum well layer is less than an energy band gap of the first quantum well layer, and an energy band gap of the third quantum well layer is equal to or less than the energy band gap of the second quantum well layer.

Abstract: Focal plane arrays and infrared detector device having a transparent common ground structure and methods of their fabrication are disclosed. In one embodiment, a front-side illuminated infrared detector device includes a contact layer and a detector structure adjacent to the contact layer. The detector structure is capable of absorbing radiation. The front-side illuminated infrared detector device further includes a common ground structure adjacent the detector structure, wherein the common ground structure is transmissive to radiation having a wavelength in a predetermined spectral band, and the common ground structure has a bandgap that is wider than a bandgap of the detector structure. The front-side illuminated infrared detector device further includes an optical layer adjacent the common ground structure.

Abstract: A stack including doped semiconductor strips, a one-dimensional array of gate electrode strips, and a dielectric matrix layer is formed over a substrate. A two-dimensional array of openings is formed through the dielectric matrix layer and the one-dimensional array of gate electrode strips. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of openings. Each of the tubular gate electrode portions is formed directly on a respective one of the gate electrode strips. Gate dielectrics are formed on inner sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surrounding gate electrodes is formed.

Abstract: A splicing screen includes: at least two display panels spliced together, each display panel having a display surface; a curved area bending towards a back side of the display surface at a splicing area; and a substantially flat area; a transparent cover disposed at a side of the display surface and covering at least the curved area of each display panel; and a plurality of support portions between the transparent cover and the curved area of each of the display panels and forming a plurality of meshes extending from the display panel to the transparent cover, an inner wall of each mesh having a reflective surface.

Abstract: A method for fabricating a semiconductor structure includes providing a substrate including a core region and a peripheral region, forming a plurality of first fin structures in the peripheral region and a plurality of second fin structures in the core region, forming a first dummy gate structure including a first dummy oxide layer and a first dummy gate electrode layer on each first fin structure, and forming a second dummy gate structure including a second dummy oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate structure and then forming a first gate oxide layer on the exposed portion of each first fin structure, and removing each second dummy gate structure. Finally, the method includes forming a first gate structure on each first fin structure and a second gate structure on each second fin structure.

Abstract: A method and apparatus wherein the method comprises: providing at least one electrode within a semiconductor layer wherein the semiconductor layer is provided on a first side of a wafer; thinning the wafer to produce a thinned wafer; providing graphene on a second side of the thinned wafer; attaching the semiconductor layer to an electrical interface on the first side of the thinned wafer; and providing at least one electrical connection from the graphene to the electrical interface so as to form a transistor comprising the at least one electrode and the graphene.

Abstract: A manufacturing method of a TFT substrate uses a top gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield can be increased to effectively improve productivity. Heavy and light ion doping can be simultaneously achieved with one single doping operation so that manufacturing cost can be reduced. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to contact the two ends of the active layer thereby effectively reducing contact resistance and improving product yield. Also provided is a TFT substrate manufactured with the method.

Abstract: An organic light-emitting diode (OLED) illuminating lamp sheet and a manufacturing method thereof are provided. The method for manufacturing an OLED illuminating lamp sheet includes: manufacturing an array substrate, the array substrate includes a first base and a first electrode formed on the first base; bonding an electrostatic film to a surface of the array substrate provided with the first electrode, forming a patterned electrostatic film by patterning the electrostatic film, and forming an organic film layer by taking the patterned electrostatic film as a mask; forming a second electrode and obtaining an OLED element; and encapsulating the OLED element and obtaining an OLED illuminating lamp sheet.

Abstract: The present invention discloses a system-level packaging method and packaging system based on 3D printing.

Abstract: A lead bonding structure includes: a plurality of leads extending outward from a package; and a plurality of electrode pads formed on a circuit board. The plurality of leads are soldered to the electrode pads, respectively. Each of the leads includes a lower wide portion having a width dimension greater than a width dimension of each of the electrode pads. The lower wide portion of each of the leads is soldered to the corresponding electrode pad.

Abstract: The present invention discloses a flexible display substrate including a first flexible substrate and a plurality of display elements disposed on a first side of the first flexible substrate, each of the display elements including a thin film transistor. The flexible display substrate further includes a plurality of protrusions each provided on a second side of the first flexible substrate opposite to the first side and corresponding to a respective thin film transistor in a thickness direction of the first flexible substrate. A projection area of each protrusion, in the thickness direction of the first flexible substrate, on the second side of the first flexible substrate at least partially overlaps with a projection area of the thin film transistor corresponding to the protrusion, in the thickness direction of the first flexible substrate, on the second side of the first flexible substrate.

Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

Abstract: A diaphragm and suspension for an electroacoustic transducer are formed by depositing a layer of compliant material on a first surface of a solid substrate and removing material from a second surface of the solid substrate. The removal leaves a block of substrate material suspended within an inner perimeter of an outer support ring of the substrate material by the compliant material, the block providing the diaphragm.

Abstract: A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.

Abstract: The present invention relates to methods of forming silicon nitride thin films on a substrate in a reaction chamber by plasma enhanced atomic layer deposition (PEALD). Exemplary methods include the steps of (i) introducing an octahalotrisilane Si3X8 silicon precursor, such as octachlorotrisilane (OCTS) Si3Cl8, into a reaction space containing a substrate, (ii) introducing a nitrogen containing plasma into the reaction space, and wherein steps (i), (ii) and any steps in between constitute one cycle, and repeating said cycles a plurality of times until an atomic layer nitride film having a desired thickness is obtained.

Abstract: A method of producing a semiconductor component is provided. The method includes providing a silicon substrate having a <111>-surface defining a vertical direction, forming in the silicon substrate at least one electronic component, forming at least two epitaxial semiconductor layers on the silicon substrate to form a heterojunction above the <111>-surface, and forming a HEMT-structure above the <111>-surface.

Abstract: Solid-state radiation transducer (SSRT) devices having buried contacts that are at least partially transparent and associated systems and methods are disclosed herein. An SSRT device configured in accordance with a particular embodiment can include a radiation transducer including a first semiconductor material, a second semiconductor material, and an active region between the first semiconductor material and the second semiconductor material. The SSRT device can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. The second contact can include a plurality of buried-contact elements electrically coupled to the second semiconductor material. Individual buried-contact elements can have a transparent portion directly adjacent to the second semiconductor material. The second contact can further include a base portion extending between the buried-contact elements, such as a base portion that is least partially planar and reflective.