Patents Examined by Abul Kalam
  • Patent number: 10120256
    Abstract: Preparation method for a thin film transistor, preparation method for an array substrate, an array substrate, and a display apparatus are provided. The preparation method for a thin film transistor includes: forming, on a pattern of a semiconductor layer, a first photoresist pattern including a photoresist with two different thicknesses, and performing a heavily-doped ion implantation process on the pattern of the semiconductor layer by using the first photoresist pattern as a barrier mask; ashing the first photoresist pattern to remove the photoresist with a second thickness and to thin the photoresist with a first thickness, so as to form a second photoresist pattern; and performing a lightly-doped ion implantation process on the pattern of the semiconductor layer by using the second photoresist pattern as a barrier mask.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: November 6, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Lulu Ye, Huafeng Liu, Jingping Lv, Lei Yang, Meng Yang, Kai Zhang, Chao Wang, Chaochao Sun, Shengwei Zhao
  • Patent number: 10096609
    Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by changing the crystalline structure to a tetragonal tungsten silicon layer.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: October 9, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicolas L. Breil, Domingo A. Ferrer, Keith Kwong Hon Wong
  • Patent number: 10095070
    Abstract: A pixel electrode or a common electrode is a light-transmissive conductive film; therefore, it is formed of ITO conventionally. Accordingly, the number of manufacturing steps and masks, and manufacturing cost have been increased. An object of the present invention is to provide a semiconductor device, a liquid crystal display device, and an electronic appliance each having a wide viewing angle, less numbers of manufacturing steps and masks, and low manufacturing cost compared with a conventional device. A semiconductor layer of a transistor, a pixel electrode, and a common electrode of a liquid crystal element are formed in the same step.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: October 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 10084051
    Abstract: A semiconductor device includes a fin structure on a substrate, device isolation patterns on the substrate at opposite sides of the fin structure, a gate electrode intersecting the fin structure and the device isolation patterns, a gate dielectric pattern between the gate electrode and the fin structure and between the gate electrode and the device isolation patterns, and gate spacers on opposite sidewalls of the gate electrode, wherein, on each of the device isolation patterns, a bottom surface of the gate dielectric pattern is at a higher level than bottom surfaces of the gate spacers.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: September 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangjine Park, Jae-Hwan Lee, Yongsun Ko
  • Patent number: 10079271
    Abstract: Provided are a mask assembly, an apparatus for manufacturing a display apparatus, and method of manufacturing a display apparatus. The mask assembly includes a mask frame and a mask sheet arranged on the mask frame. The mask sheet includes a pattern portion configured to allow a deposition material to pass through an opening of the pattern portion. The pattern portion is recessed from a surface of the mask sheet. In addition, an outermost edge of the pattern portion is uneven.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: September 18, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jaesik Kim, Taemin Kang, Jeongkuk Kim, Youngsuk Cho
  • Patent number: 10079326
    Abstract: An exemplary embodiment of the present invention provides an optical sensor, including: a substrate; an infrared ray sensing thin film transistor including a first semiconductor layer that is formed on the substrate and arranged to operate by receiving infrared light, and a bandpass filter formed on the substrate and sized and arranged to pass the infrared light; a visible ray sensing thin film transistor including a second semiconductor layer formed on the substrate and arranged to operate by receiving visible light; and a switching thin film transistor including a third semiconductor layer formed on the substrate, wherein the bandpass filter may be formed of a metal material patterned to have features, successive features spaced apart from each other by a predetermined period so as to pass the infrared light and to block the visible light.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 18, 2018
    Assignee: Samsung Display Co. Ltd.
    Inventors: Yun Jong Yeo, Jung Ha Son, Joo Hyung Lee
  • Patent number: 10074675
    Abstract: A thin film transistor substrate includes a substrate; a first thin film transistor on the substrate and including a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor on the substrate and including a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode; an intermediate insulating layer on the first gate electrode and the second gate electrode and under the oxide semiconductor layer; and a dummy layer between the first source electrode and the intermediate insulating layer and between the first drain electrode and the intermediate insulating layer, wherein the dummy layer is formed of a same material as the oxide semiconductor layer.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: September 11, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Hyunsoo Shin, Uijin Chung
  • Patent number: 10074556
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: September 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Masaaki Shinohara, Shigeo Tokumitsu
  • Patent number: 10053358
    Abstract: A microelectromechanical systems (MEMS) structure includes a substrate, an epitaxial polysilicon cap located above the substrate, a first cavity portion defined between the substrate and the epitaxial polysilicon cap, and a first graphene component having at least one graphene surface immediately adjacent to the first cavity portion.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: August 21, 2018
    Assignee: Robert Bosch GmbH
    Inventors: Gary Yama, Seow Yeun Yee, Franz Laermer, Ashwin Samarao
  • Patent number: 10056407
    Abstract: A semiconductor device includes a first gate structure disposed on a substrate. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode and first sidewall spacers disposed on both side faces of the first gate electrode and the first cap insulating layer. The semiconductor device further includes a first protective layer formed over the first cap insulating layer and at least one of the first sidewall spacers. The first protective layer includes at least one selected from the group consisting of AlON, AlN and amorphous silicon.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Hsiang-Ku Shen, Yu-Lien Huang, Wilson Huang, Janet Chen, Jeng-Ya David Yeh
  • Patent number: 10032684
    Abstract: A lead bonding structure includes: a plurality of leads extending outward from a package; and a plurality of electrode pads formed on a circuit board. The plurality of leads are soldered to the electrode pads, respectively. Each of the leads includes a lower wide portion having a width dimension greater than a width dimension of each of the electrode pads. The lower wide portion of each of the leads is soldered to the corresponding electrode pad.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: July 24, 2018
    Assignee: Japan Aviation Electronics Industry, Ltd.
    Inventors: Hiroshi Akimoto, Takushi Yoshida
  • Patent number: 10008593
    Abstract: A semiconductor device includes a well region of a first conductivity type, having a first depth, formed in a substrate. A source contact region of a second conductivity type is formed in the well region. A drift region of the second conductivity type, having a second depth greater than 50% of the first depth, is formed in the substrate adjacent to the well region. A drain contact region of the second conductivity type is formed in the drift region. A gate electrode is formed on the substrate between the source contact region and the drain contact region. The drain contact region is spaced apart from the gate electrode and the source contact region is adjacent to the gate electrode. Furthermore, a method of fabricating a semiconductor device is also provided. The method includes performing a multi-step implantation process to form a drift region.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 26, 2018
    Assignee: MediaTek Inc.
    Inventors: Chih-Chung Chiu, Puo-Yu Chiang
  • Patent number: 10008532
    Abstract: A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate and extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and two end cap hardmasks are between the gate dielectric and the gate electrode over the implant isolation region. The two end cap hardmasks include same dopants as those implanted into the active region.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Wen-De Wang, Wen-I Hsu
  • Patent number: 10003022
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming Chyi Liu, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 9997632
    Abstract: A fin-type field effect transistor device including a substrate, at least one gate stack structure, spacers and source and drain regions is described. The gate stack structure is disposed on the substrate and the spacers are disposed on sidewalls of the gate stack structure. The source and drain regions are disposed in the substrate and located at opposite sides of the gate stack structures. A dielectric layer having contact openings is disposed over the substrate and covers the gate stack structures. Metal connectors are disposed within the contact openings and connected to the source and drain regions, and adhesion layers are sandwiched between the contact openings and the metal connectors located within the contact openings.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 9978784
    Abstract: A device includes a semiconductor substrate, which has a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A first and a second grid line are parallel to each other, and are disposed on the backside of, and overlying, the semiconductor substrate. A stacked layer includes an adhesion layer, a metal layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Szu-An Wu, Sheng-Wen Chen
  • Patent number: 9978764
    Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: May 22, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
  • Patent number: 9972712
    Abstract: A semiconductor device according to an embodiment includes a conductive region including titanium (Ti), oxygen (O), at least one first element from zirconium (Zr) and hafnium (Hf), and at least one second element from vanadium (V), niobium (Nb), and tantalum (Ta), an n-type first SiC region, a p-type second SiC region provided between the conductive region and the n-type first SiC region, a gate electrode, and a gate insulating layer provided between the conductive region, the p-type second SiC region, the n-type first SiC region, and the gate electrode.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 15, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Ryosuke Iijima
  • Patent number: 9966460
    Abstract: A switching device includes a semiconductor substrate having a first element range and an ineffective range. First trenches extend in a first direction across the first element range and the ineffective range. Second trenches are provided in each inter-trench region within the first element range and are not provided within the ineffective range. A gate electrode is disposed in the trenches. No contact hole is provided in an interlayer insulating film within the ineffective range. The first metal layer covers the interlayer insulating film. The insulating protective film covers a portion of the first metal layer on its outer peripheral side within the ineffective range. The second metal region is in contact with the first metal layer within an opening of the insulating protective film, and is in contact with a side surface of the opening.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: May 8, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka Soeno, Takashi Kuno
  • Patent number: 9954002
    Abstract: Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: April 24, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hongmei Li, Junjun Li