Patents Examined by Adam M Queler
  • Patent number: 9348743
    Abstract: A cache controller includes a first register that updates after every memory location swap operation on a number of cache sets in a cache memory and resets every N?1 memory location swap operations. N is a number of the cache sets in the cache memory. The memory controller also has a second register that updates after every N?1 memory location swap operations, and resets every (N2?N) memory location swap operations. The first and second registers track a relationship between logical locations and physical locations of the cache sets.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: May 24, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventor: Xiangyu Dong
  • Patent number: 9348762
    Abstract: A tag unit configured to manage a cache unit includes a coalescer that implements a set hashing function. The set hashing function maps a virtual address to a particular content-addressable memory unit (CAM). The coalescer implements the set hashing function by splitting the virtual address into upper, middle, and lower portions. The upper portion is further divided into even-indexed bits and odd-indexed bits. The even-indexed bits are reduced to a single bit using a XOR tree, and the odd-indexed are reduced in like fashion. Those single bits are combined with the middle portion of the virtual address to provide a CAM number that identifies a particular CAM. The identified CAM is queried to determine the presence of a tag portion of the virtual address, indicating a cache hit or cache miss.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 24, 2016
    Assignee: NVIDIA Corporation
    Inventors: Brian Fahs, Eric T. Anderson, Nick Barrow-Williams, Shirish Gadre, Joel James McCormack, Bryon S. Nordquist, Nirmal Raj Saxena, Lacky V. Shah
  • Patent number: 9342462
    Abstract: A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit may multiply bit vectors representing key values by a sparse bit matrix and may add a constant bit vector to the results. The hash function sub-circuits may be constructed using odd-parity circuits that accept as inputs subsets of the bits of the bit vectors representing the key values. The sparse bit matrices may be chosen or generated so that there are at least twice as many 0-bits per row as 1-bits or there is an upper bound on the number of 1-bits per row. Using sparse bit matrices in the hash function sub-circuits may allow the lookup circuit to perform lookup operations with very low latency.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: May 17, 2016
    Assignee: Oracle International Corporation
    Inventors: Guy L. Steele, Jr., David R. Chase
  • Patent number: 9342255
    Abstract: A method of monitoring, optimizing, and dynamically varying transfer size in a storage device is provided, including: receiving data transfer parameters for a Solid State Disk (SSD) device; selecting a data transfer size from the disk characterization data associated with the SSD device, based on a SSD device identifier in the received data transfer parameters matching the SSD device identifier in the disk characterization data; searching a weight-age table for a process identifier (PID) matching the PID from the received data transfer parameters; determining a heuristic representing a statistical distribution of Input/Output (I/O) operations per second (IOPS) and transfer sizes over time; modifying the received data transfer parameters based on at least one of: the selected data transfer size from the disk characterization data; the weight-age table; and the heuristic; and completing one or more (I/O) operations with the SSD device using the modified data transfer parameters.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: May 17, 2016
    Assignee: International Business Machines Corporation
    Inventors: Prasanna Jayaraman, Abhijit Saurabh, M. Dean Sciacca, Janani Swaminathan, Gary A. Tressler
  • Patent number: 9342463
    Abstract: A processor, operable in a computing storage environment, for each rank in a storage management device in the computing storage environment, allocates a lower maximum count, and a higher maximum count, of Task Control Blocks (TCBs) to be implemented for performing a storage operation, and performs the storage operation using up to the lower maximum count of TCBs, yet only allows those TCBs above the lower maximum count to be allocated for performing the storage operation satisfying at least one criterion.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: May 17, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Michael T. Benhase, Lokesh M. Gupta, Kenneth W. Todd
  • Patent number: 9336150
    Abstract: A controller receives a request to perform staging or destaging operations with respect to an area of a cache. A determination is made as to whether one or more discard scans are being performed or queued for the area of the cache. In response to determining that one or more discard scans are being performed or queued for the area of the cache, the controller avoids satisfying the request to perform the staging or the destaging operations with respect to the area of the cache.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: May 10, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Benhase, Lokesh M. Gupta, Matthew J. Kalos
  • Patent number: 9335945
    Abstract: A method of monitoring, optimizing, and dynamically varying transfer size in a storage device is provided, including: receiving data transfer parameters for a Solid State Disk (SSD) device; selecting a data transfer size from the disk characterization data associated with the SSD device, based on a SSD device identifier in the received data transfer parameters matching the SSD device identifier in the disk characterization data; searching a weight-age table for a process identifier (PID) matching the PID from the received data transfer parameters; determining a heuristic representing a statistical distribution of Input/Output (I/O) operations per second (IOPS) and transfer sizes over time; modifying the received data transfer parameters based on at least one of: the selected data transfer size from the disk characterization data; the weight-age table; and the heuristic; and completing one or more (I/O) operations with the SSD device using the modified data transfer parameters.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: May 10, 2016
    Assignee: International Business Machines Corporation
    Inventors: Prasanna Jayaraman, Abhijit Saurabh, M. Dean Sciacca, Janani Swaminathan, Gary A. Tressler
  • Patent number: 9336153
    Abstract: A computer system, comprising a server on which an application runs, and a storage system that stores data to be used by the application, the cache driver being configured to change, in a case of the condition of a cache area is a first cache condition in which data is readable from a cache area and writing of data into the cache area is prohibited, the condition of the cache area to a third cache condition in which reading of data from the cache area is prohibited and writing of data into the cache area is prohibited, from the first cache condition.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: May 10, 2016
    Assignee: HITACHI, LTD.
    Inventors: Ken Sugimoto, Yuusuke Fukumura, Nobukazu Kondo
  • Patent number: 9335942
    Abstract: Methods and structure for masking of logical unit numbers (LUNs) within a switching device coupled with one or more storage enclosures. Each storage enclosure defines one or more logical volumes each identified by a LUN within the storage enclosures. The switching device gathers LUN definition information regarding each LUN defined by each storage enclosure coupled with the switching device. LUN access permission information may be provided by an administrative node/user defining a level of access permitted or denied for each host system for each LUN for each storage enclosure. The switching device then intercepts a REPORT LUNS command from any host directed to a storage enclosure and responds with only those LUNs to which the requesting host system has permitted access. Further, any other SCSI command intercepted at the switching device directed to a LUN to which the host system does not have access is modified to identify an invalid LUN.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: May 10, 2016
    Assignee: Avago Technologies General IP (Technologies) Pte. Ltd.
    Inventors: Umang Kumar, Nishant Kumar Yadav, Abhijit Suhas Aphale
  • Patent number: 9329896
    Abstract: Exemplary methods, apparatuses, and systems receive a first request for a storage address at a first access time. Entries are added to first and second data structures. Each entry includes the storage address and the first access time. The first data structure is sorted in an order of storage addresses. The second data structure is sorted in an order of access times. A second request for the storage address is received at a second access time. The first access time is determined by looking up the entry in first data structure using the storage address received in the second request. The entry in the second data structure is looked up using the determined first access time. A number of entries in second data structure that were subsequent to the second entry is determined. A hit count for a reuse distance corresponding to the determined number of entries is incremented.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: May 3, 2016
    Assignee: VMware, Inc.
    Inventors: Sachin Manpathak, Mustafa Uysal, Puneet Zaroo, Ricardo Koller, Luis Useche
  • Patent number: 9329987
    Abstract: System and methods are provided for dynamically determining accesses to memory areas in a memory system. An example system includes a first plurality of tracking units, a second plurality of tracking units, and a controller. The first plurality of tracking units are configured to determine accesses to multiple memory areas during a first time period and select one of the memory areas based at least in part on the determined accesses to the memory areas, a memory area including multiple sub-areas. The second plurality of tracking units are configured to determine accesses to the sub-areas of the selected memory area during a second time period. The controller is configured to generate information related to the determined accesses to the memory areas and the sub-areas in the selected memory area for memory management.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 3, 2016
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Jun Zhu, Ofer Zaarur
  • Patent number: 9323676
    Abstract: Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: April 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy C. Bronson, Garrett M. Drapala, Rebecca M. Gott, Pak-Kin Mak, Vijayalakshmi Srinivasan, Craig R. Walters
  • Patent number: 9323695
    Abstract: Systems and methods for predictive cache replacement policies are provided. In particular, some embodiments dynamically capture and predict access patterns of data to determine which data should be evicted from the cache. A novel tree data structure can be dynamically built that allows for immediate use in the identification of developing patterns and the eviction determination. In some cases, the data can be dynamically organized into histograms, strings, and other representations allowing traditional analysis techniques to be applied. Data organized into histogram-like structures can also be converted into strings allowing for well-known string pattern recognition analysis. The pattern recognition and prediction techniques disclosed also have applications outside of caching.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: April 26, 2016
    Assignee: FACEBOOK, INC.
    Inventor: Eitan Frachtenberg
  • Patent number: 9317375
    Abstract: A method is used for managing cache backup and restore for continuous data replication and protection. I/O operations are quiesced at a cache module. A first snapshot of a storage object and a second snapshot of an SSD cache object are taken. The I/O operations at the cache module are unquiesced. A single backup image comprising the first snapshot and the second snapshot is created. The single backup image is sent to a first data protection appliance (DPA) and recorded in a journal.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 19, 2016
    Assignee: LENOVOEMC LIMITED
    Inventors: Vamsikrishna Sadhu, Brian R. Gruttadauria, Suresh Kumar Kalidindi
  • Patent number: 9317417
    Abstract: A device may receive information identifying an attribute to be used when determining whether to archive a digital message. The attribute may be associated with the digital message. The device may determine an attribute value based on the attribute and the digital message. The device may determine an archival weight corresponding to the attribute. The device may compute an archival score for the digital message. The archival score may be based on the attribute value and the archival weight. The device may determine that the archival score satisfies a threshold. The device may archive the digital message based on determining that the archival score satisfies the threshold.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: April 19, 2016
    Assignee: VERIZON PATENT AND LICENSING INC.
    Inventors: Anthony Lemus, James T. McConnell
  • Patent number: 9318154
    Abstract: Systems and methods for reducing problems and disadvantages associated with protecting data during cold excursions are provided. A method for preventing unreliable data operations at cold temperatures may include determining whether a first temperature of a solid state drive (SSD) is below a threshold temperature. The method may also include initiating an artificial read/write operation if the first temperature is below the threshold temperature.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: April 19, 2016
    Assignee: Dell Products L.P.
    Inventor: Clinton Allen Powell
  • Patent number: 9317217
    Abstract: Systems and methods for wiping and verifying the wiping of a data storage device where the dirtying of blocks of the storage device is tracked and only the dirtied blocks are scanned to verify if the storage device has been sufficiently wiped.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: April 19, 2016
    Assignee: Amazon Technologies, Inc.
    Inventor: Eden G. Adogla
  • Patent number: 9311098
    Abstract: A mechanism for reducing power consumption of a cache memory of a processor includes a processor with a cache memory that stores instruction information for one or more instruction fetch groups fetched from a system memory. The cache memory may include a number of ways that are each independently controllable. The processor also includes a way prediction unit. The way prediction unit may enable, in a next execution cycle, a given way within which instruction information corresponding to a target of a next branch instruction is stored in response to a branch taken prediction for the next branch instruction. The way prediction unit may also, in response to the branch taken prediction for the next branch instruction, enable, one at a time, each corresponding way within which instruction information corresponding to respective sequential instruction fetch groups that follow the next branch instruction are stored.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: April 12, 2016
    Assignee: Apple Inc.
    Inventors: Ronald P. Hall, Conrado Blasco-Allue
  • Patent number: 9311248
    Abstract: Embodiments of a method and apparatus for monitoring activity on a virtual machine are generally described herein. The activity may be monitored by a first hypervisor and the virtual machine may be controlled by a second hypervisor. In some embodiments, the method includes setting a breakpoint in a kernel function of the virtual machine. The method may further include generating a page fault, responsive to the virtual machine halting execution at the breakpoint, to cause the second hypervisor to page in contents of a memory location accessed by the kernel function. The method may further include inspecting the contents of the memory location to detect activity in the virtual machine.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: April 12, 2016
    Assignee: Raytheon Cyber Products, LLC
    Inventor: John R. Wagner
  • Patent number: 9311988
    Abstract: A row buffer 102 in DRAM 100 stores any data read from a memory array 101 in a specified data length unit. An LLC 206 is cache memory, and extracts and stores a part of data stored in the row buffer 102 as cache data. In a MAC 701, when push-out control of the LLC 206 is performed, it is predicted that data at which DIMM address is stored in the row buffer 102 in the near future based on the queuing state of an MRQ 203. In the MAC 701, each physical address of the cache data in a push-out target range 702 on the LLC 206 is converted into a DIMM address. If the converted address matches the predicted address of the data, then the cache data corresponding to the matching addresses is pushed out on a priority basis from the LLC 206.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: April 12, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takatsugu Ono, Takeshi Shimizu