Abstract: For combining virtual mapping metadata and physical space mapping metadata in a storage system by a processor device in a computing environment, data and metadata are maintained into separate virtual streams. The separate virtual streams include a metadata stream for the metadata and a data stream for the data. Metadata for each input/output (I/O) operation received is determined using a linear function operation, the function operation being an offset of the metadata in the metadata stream that is equal to the I/O operation multiplied by a maximal metadata ratio. The metadata is allocated on the metadata stream and the metadata stream is divided into fixed size block that is responsible for describing a size of a logical space, where the logical space is equal to one divided by the maximal metadata ratio, and it is determined if the metadata has been previously loaded.

Abstract: A memory control method for a computer system is provided. The method includes the steps of: (a) calculating an operation cost of each of given M memory objects in each of N memory regions, M being an integer larger than 0, wherein the operation cost is a quantifiable parameter of a said memory region with respect to a said memory object operating therein; (b) determining an optimized allocation of the M memory objects in the N memory regions according to the calculated operation cost of each of the M memory objects in each of the N memory regions.

Abstract: Systems and methods for verifying the wiping of a storage device using one of either a partial scan verification or a full scan verification, wherein a partial scan verification may be conducted based on at least one metric associated with the storage device and a threshold value for the at least one metric.

Abstract: Embodiments of the invention are directed to optimizing reconstruction of operation data in volatile memory of solid-state storage subsystems. In various embodiments, operation data is stored in the volatile memory with persistent backup data of the operation data in the non-volatile memory. In one embodiment, operation data includes a superblock table that is used to identify most or all groups of blocks (superblocks) within the storage device that certain firmware components operate on. Sometimes operation data in the volatile memory is lost or corrupted due to a power interruption or system shutdown. To optimize the reconstruction of the superblock table or other similar operation data in the volatile memory, embodiments of the invention use a “snapshot entry” to identify the latest entry information, allowing the controller to quickly identify the most updated physical locations of the operation data portions and complete the reconstruction in an efficient manner.

Abstract: According to the present invention, it is possible to construct a backup configuration of a particular application data, without influencing data of another application. A management computer is coupled to a host computer on which an application operates, and to a storage apparatus that includes a plurality of volume groups each having one or more logical volumes. At least one of the logical volumes is allocated to the application. The management computer includes a volume group overlapping use determination part and a backup policy determination part. When the backup of the volume group to which one logical volume belongs is configured, the volume group overlapping use determination part determines whether there is another application that uses the volume group. The backup policy determination part determines whether there is set, for another volume group, backup policy information same as that set for the application.

Abstract: A first RAID module is added to a first RAID controller and a second RAID module is added to a second RAID controller. An array of physical disks is partitioned into two partitions across the array of physical disks. The first partition is assigned to the first RAID module and the second partition is exposed to the second RAID module. Each of the RAID modules exposes their respective partitions to their associated RAID controller as a single array. Each RAID module further receives I/O from its respective RAID controller, and translates the I/O to access its associated partition.

Abstract: Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.

Abstract: A processor includes a front end, a cache, and a cache controller. The front end includes logic to receive an instruction defining a priority dataset. The priority dataset includes ranges of memory addresses each corresponding to a respective priority level. The cache controller includes logic to detect a miss in the cache for a requested cache value, determine a candidate cache victim from the cache, determine a priority of the requested cache value and the candidate cache victim according to the priority dataset, and evict the candidate cache victim based on a determination that the priority of the candidate cache victim is less or equal to the priority of the requested cache value.

Abstract: A system and method for implementing memory overlays for portable pointer variables. The method includes providing a program executable by a heterogeneous processing system comprising a plurality of a processors running a plurality of instruction set architectures (ISAs). The method also includes providing a plurality of processor specific functions associated with a function pointer in the program. The method includes executing the program by a first processor. The method includes dereferencing the function pointer by mapping the function pointer to a corresponding processor specific feature based on which processor in the plurality of processors is executing the program.

Abstract: An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access. An input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros. As connection interconnects, command information interconnects and data interconnects are included. The command information interconnects are formed by private interconnects, while the data interconnects are formed by private interconnects for at least the second direction interconnects.

Abstract: Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.

Abstract: A coherent attached processor proxy (CAPP) of a primary coherent system receives a memory access request specifying a target address in the primary coherent system from an attached processor (AP) external to the primary coherent system. The CAPP includes a CAPP directory of contents of a cache memory in the AP that holds copies of memory blocks belonging to a coherent address space of the primary coherent system. In response to the memory access request, the CAPP performs a first determination of a coherence state for the target address and allocates a master machine to service the memory access request in accordance with the first determination. Thereafter, during allocation of the master machine, the CAPP updates the coherence state and performs a second determination of the coherence state. The master machine services the memory access request in accordance with the second determination.

Abstract: A memory formatting method adapted to a memory storage apparatus is provided. The memory formatting method includes configuring a plurality of logical block addresses to be mapped to a portion of a plurality of physical blocks, generating a first file system data and a second file system data according to the size of the logical block addresses, and storing the first file system data into a first physical block, and the first physical block is mapped to a first logical block address among the logical block addresses. The memory formatting method also includes selecting a second physical block among the physical blocks, storing the second file system data into the second physical block, determining whether a format command is received, and when the format command is received, re-mapping the first logical block address to the second physical block.

Abstract: A system and method for providing memory device readiness to a memory controller is disclosed. One example system includes a channel controller operably connected to a memory controller and a group of flash memory devices. The channel controller may receive, from the memory controller a request for a status of one or more memory devices in the group of flash memory devices. The channel controller may determine the status of the one or more memory devices, the status being determined while the memory controller is permitted to execute one or more other commands related to one or more other memory devices in a different group of memory devices. On determining that the one or more memory devices are in a ready status, the channel controller may provide the ready status to the memory controller.

Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

Abstract: A method for data storage in a data storage system, which includes a main storage device and a non-volatile memory, includes assessing quality levels of respective memory blocks of the non-volatile memory. One or more of the memory blocks whose assessed quality levels are lower than a predefined quality threshold are identified. The identified memory blocks are assigned to serve as read cache memory. Data is read from the main storage device via the read cache memory, including the assigned memory blocks.

Abstract: A register file device includes: a multi-port latch; and a write circuit that generates a signal to be written in the multi-port latch, the write circuit generating the signal on the basis of a plurality of data groups each including a write control signal, a write address, and a piece of write data, wherein the write circuit includes: a detection circuit that detects at least two write control signals occurred simultaneously among write control signals, and a changing circuit that changes write data corresponding to one of the write control signal to become same as write data corresponding to another of the write control signal.

Abstract: A computer-implemented method, computer program product and computing system for moving at least a portion of cache data from a first cache storage device coupled to a first computing device included within a first virtual machine to a shared storage device. The at least a portion of cache data is moved from the shared storage device to a second cache storage device coupled to a second computing device included within a second virtual machine.

Abstract: A processor, operable in a computing storage environment, for each rank in a storage management device in the computing storage environment, allocates a lower maximum count, and a higher maximum count, of Task Control Blocks (TCBs) to be implemented for performing a storage operation, and performs the storage operation using up to the lower maximum count of TCBs, yet only allows those TCBs above the lower maximum count to be allocated for performing the storage operation satisfying at least one criterion.

Abstract: A computer-implemented method, computer program product and computing system for defining a cache storage portion within a cache storage device coupled to a computing device. An application storage portion is defined within the cache storage device coupled to the computing device. The cache storage portion is configured to store cache data and the application storage portion is configured to store application data.