Patents Examined by Adam S Bowen
  • Patent number: 11641758
    Abstract: A display device may include a hole, a display element, a switching element, a groove, a planarization layer, and a cover layer. The switching element may be electrically connected to the display element. The encapsulation layer may cover the display element. The groove may be located between the hole and the display element. A portion of the planarization layer may be located between a first edge of the planarization layer and a second edge of the planarization and may be located in the groove. The first edge of the planarization layer may be located closer to the display element than the second edge of the planarization layer. The cover layer may at least partially cover the first edge of the planarization layer.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: May 2, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dongjin Moon, Yeri Jeong, Inyoung Han
  • Patent number: 11631744
    Abstract: Disclosed are a semiconductor structure and a forming method thereof.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: April 18, 2023
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Jisong Jin
  • Patent number: 11630212
    Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes: a substrate made by a first material or a first material-composite; an absorption layer made by a second material or a second material-composite, the absorption layer being supported by the substrate and the absorption layer including: a first surface; a second surface arranged between the first surface and the substrate; and a channel region having a dopant profile with a peak dopant concentration equal to or more than 1×1015 cm?3, wherein a distance between the first surface and a location of the channel region having the peak dopant concentration is less than a distance between the second surface and the location of the channel region having the peak dopant concentration, and wherein the distance between the first surface and the location of the channel region having the peak dopant concentration is not less than 30 nm.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: April 18, 2023
    Assignee: Artilux, Inc.
    Inventors: Szu-Lin Cheng, Chien-Yu Chen, Shu-Lu Chen, Yun-Chung Na, Ming-Jay Yang, Han-Din Liu, Che-Fu Liang, Jung-Chin Chiang, Yen-Cheng Lu, Yen-Ju Lin
  • Patent number: 11631764
    Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: April 18, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenichi Hisada, Koichi Arai, Hironobu Miyamoto
  • Patent number: 11626545
    Abstract: A light emitting device is disclosed. In an embodiment a light-emitting device includes a pixel comprising at least three sub-pixels, wherein the at least three sub-pixel include a first sub-pixel including a first conversion element, wherein the first conversion element includes a green phosphor, a second sub-pixel including a second conversion element, wherein the second conversion element includes a red phosphor and a third sub-pixel free of a conversion element, wherein the third sub-pixel is configured to emit blue primary radiation, wherein each sub-pixels has an edge length of at most 100 ?m, and wherein the pixel is a linear chain of sub-pixels and a plurality of pixels is arranged in a two dimensional ordered pattern so that a first sub-pixel is never adjacent to a third sub-pixel in a vertical direction and in a horizontal direction of the ordered pattern.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: April 11, 2023
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Benjamin Daniel Mangum, David O'Brien, Britta Göötz
  • Patent number: 11616193
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 28, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Chen-Yi Weng, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen
  • Patent number: 11610994
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kun-Mu Li, Hsueh-Chang Sung
  • Patent number: 11605617
    Abstract: A light emitting device includes: a substrate including a base member including an upper surface, a lower surface and one or more lateral surfaces, and defining a recess that is opened at the upper surface and the lateral surfaces and surrounds an outer perimeter of the upper surface; a first light emitting element; a second light emitting element; a light guide member covering the first and the second light emitting elements and the upper surface of the base member; and a first reflective member having a closed-ring shape surrounding the upper surface of the base member and the light guide member, a portion of the first reflective member being located in the recess. At least one of the lateral surfaces of the base member and corresponding at least one of one or more outer lateral surfaces of the first reflective member are in the same plane.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 14, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Takuya Nakabayashi, Yukiko Yokote
  • Patent number: 11600618
    Abstract: A includes depositing a gate electrode layer over a semiconductor substrate; patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion; forming a first gate spacer alongside the first gate electrode; patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first spacer.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Li-Feng Teng, Wei-Cheng Wu, Fang-Lan Chu, Ya-Chen Kao
  • Patent number: 11600624
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first dielectric fin, a first semiconductor fin and a second dielectric fin over a substrate. The first semiconductor fin interposes between and is spaced apart from the first dielectric fin and the second dielectric fin. The semiconductor structure also includes a first source/drain structure over a source/drain portion of the first semiconductor fin, an inter-layer dielectric layer covering a first portion of an upper surface of the first source/drain structure and an upper surface of the second dielectric fin, and a first contact in the inter-layer dielectric layer and covering a second portion of the upper surface of the first source/drain structure and an upper surface of the first dielectric fin.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11600534
    Abstract: A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Min Liu, Hsueh-Chang Sung, Li-Li Su, Yee-Chia Yeo
  • Patent number: 11588054
    Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: February 21, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soonmoon Jung, Daewon Ha, Sungmin Kim, Hyojin Kim, Keun Hwi Cho
  • Patent number: 11581432
    Abstract: The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: February 14, 2023
    Assignee: IPOWER SEMICONDUCTOR
    Inventor: Hamza Yilmaz
  • Patent number: 11581411
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in an NMOS region, a second source/drain epitaxial feature disposed in the NMOS region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a third source/drain epitaxial feature disposed in a PMOS region, a second dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature, and a conductive feature disposed over the first, second, and third source/drain epitaxial features and the first and second dielectric features.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. More, Jia-Ying Ma, Cheng-Han Lee
  • Patent number: 11581321
    Abstract: Integrated circuit (“IC”) layouts are disclosed for improving performance of memory arrays, such as static random access memory (“SRAM”). An exemplary IC device includes an SRAM cell and an interconnect structure electrically coupled to the SRAM cell. The interconnect structure includes a first metal layer electrically coupled to the SRAM cell that includes a bit line, a first voltage line having a first voltage, a word line landing pad, and a second voltage line having a second voltage that is different than the first voltage. The first voltage line is adjacent the bit line. The word line landing pad is adjacent the first voltage line. The second voltage line is adjacent the word line landing pad. A second metal layer is disposed over the first metal layer. The second metal layer includes a word line that is electrically coupled to the word line landing pad.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11574916
    Abstract: A method for manufacturing a semiconductor device includes etching a substrate to form a semiconductor fin. An isolation structure is formed above the substrate and laterally surrounds the semiconductor fin. A fin sidewall structure is formed above the isolation structure and on a sidewall of the semiconductor fin. The semiconductor fin is recessed to expose an inner sidewall of the fin sidewall structure. A source/drain epitaxial structure is grown on the recessed semiconductor fin.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu, Kun-Mu Li
  • Patent number: 11569223
    Abstract: A method for fabricating an integrated circuit is provided. The method includes etching a first recess in a semiconductor structure; forming a first doped epitaxial feature in the first recess; and forming a second doped epitaxial feature over the first doped epitaxial feature, wherein the second doped epitaxial feature has a conductive type opposite to a conductive type of the first doped epitaxial feature.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tao-Yi Hung, Wun-Jie Lin, Jam-Wem Lee, Kuo-Ji Chen, Chia-En Huang
  • Patent number: 11569084
    Abstract: A method for removing nodule defects is disclosed. The nodule defects may be formed on a non-selected portion of a semiconductor structure during formation of a semiconductor region on a selected portion of the semiconductor structure. A plasma having a higher selectivity to etch the nodule defects relative to the semiconductor region may be used to selectively remove the nodule defects on the non-selected portion.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Yu Lin, Chih-Chiang Chang, Chien-Hung Chen, Ming-Hua Yu, Tsung-Hsi Yang, Ting-Yi Huang, Chii-Horng Li, Yee-Chia Yeo
  • Patent number: 11562994
    Abstract: A MOS IC includes a first circuit including a first plurality of nMOS devices, a first p-tap cell, and a first dummy nMOS cell, and a second circuit including a first plurality of pMOS devices, a first dummy pMOS cell, and a first n-tap cell. The nMOS/pMOS devices are spaced apart in a first direction. The first p-tap cell and the first dummy nMOS cell are adjacent to each other in the first direction between the nMOS devices. The first dummy pMOS cell and the first n-tap cell are adjacent to each other in the first direction between the pMOS devices. The pMOS devices are adjacent to the nMOS devices in a second direction orthogonal to the first direction. The first p-tap cell/the first dummy pMOS cell and the first dummy nMOS cell/the first n-tap cell are respectively adjacent to each other in the second direction.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: January 24, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kaushik Baruah, Thomas Hua-Min Williams
  • Patent number: 11557518
    Abstract: A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: January 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-En Lin, Chi On Chui, Fang-Yi Liao, Chunyao Wang, Yung-Cheng Lu