Abstract: A semiconductor device includes first and second metal-insulator-metal structures. The first metal-insulator-metal structure includes a first bottom conductor plate, a first portion of a first dielectric layer, a first middle conductor plate, a first portion of a second dielectric layer, and a first top conductor plate stacked up one over another. The second metal-insulator-metal structure includes a second bottom conductor plate, a second portion of the first dielectric layer, a second middle conductor plate, a second portion of the second dielectric layer, and a second top conductor plate stacked up one over another. In a cross-sectional view, the first bottom conductor plate is wider than the first middle conductor plate that is wider than the first top conductor plate, and the second bottom conductor plate is narrower than the second middle conductor plate that is narrower than the first top conductor plate.

Abstract: Semiconductor assemblies and packages using edge stacking and associated systems and methods are disclosed herein. A semiconductor package may include (1) a base substrate having a base surface, (2) one or more dies attached over the base surface, and (3) a mold material encapsulating the base substrate and the one or more dies. The package may further include connectors on a side surface thereof, wherein the connectors are electrically coupled to the base substrate and/or the one or more dies. The connectors may be further configured to electrically couple the package to one or more neighboring semiconductor packages and/or electrical circuits.

Abstract: Embodiments of semiconductor devices and methods for forming the same are disclosed. In an example, a semiconductor device includes at least one dielectric layer pair including a first dielectric layer and a second dielectric layer different from the first dielectric layer, an interlayer dielectric (ILD) layer in contact with the at least one dielectric layer pair, and one or more capacitors each extending vertically through the ILD layer and in contact with the at least one dielectric layer pair.

Abstract: The present invention provides a display panel in which deterioration of color tone may be suppressed regardless of the reflectance of the display element.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a photodetector disposed within a substrate. A grid structure is disposed over the substrate and the photodetector. A conductive layer is disposed between the grid structure and the substrate. A conductive contact extends into an upper surface of the substrate. The conductive layer is directly electrically coupled to the conductive contact.

Abstract: The present technology relates to a solid-state imaging device compatible with miniaturization of pixels, a method for manufacturing the solid-state imaging device, and an electronic apparatus. The solid-state imaging device is formed by joining a front surface side as the wiring layer formation surface of the first semiconductor substrate to a back surface side of the second semiconductor substrate. The first semiconductor substrate includes a photodiode and a transfer transistor. The second semiconductor substrate includes a charge/voltage retention portion that retains the electric charge transferred by the transfer transistor or the voltage corresponding to the electric charge. The solid-state imaging device includes a through electrode that penetrates the second semiconductor substrate, and transmits the electric charge or the voltage to the charge/voltage retention portion. The present technology can be applied to solid-state imaging devices and the like, for example.

Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.

Abstract: The present invention discloses a pixel structure of a stacked image sensor and a preparation method thereof, by bonding processes to stack a first silicon wafer to a third silicon wafer up and down; wherein, a first photodiode array is set on the first silicon wafer located in middle, and a second photodiode array is provided on the second silicon wafer located above, and the surface of each the second photodiode in the second photodiode array is aligned and bonded correspondingly with the surface of each the first photodiode in the first photodiode array, so as to form a chip of the pixel structure of the stacked image sensor with a very deep junction depth, which is particularly suitable for near-infrared sensitization, and can effectively improve quantum efficiency in near-infrared wave bands; and by adopting a backlight technology, incident lights irradiating to photodiodes are not affected by the metal interconnect layers, both of sensitive and fill factor are high, especially for small-size pixels, whi

Abstract: A method includes disposing a plurality of active solder pads and at least one mechanical support solder pad on the substrate. The plurality of active solder pads provide areas for mechanical bonding of the substrate to at least one device contact pad disposed on a semiconductor die. The at least one mechanical support solder pad provides an area for mechanical bonding of the substrate to at least one dummy device contact pad disposed on the semiconductor die. The method further includes mechanically bonding the substrate to the semiconductor die by forming solder joints between the plurality of active solder pads and the at least one device contact pad, and between the at least one mechanical support pad and the at least one dummy device contact pad.

Abstract: A temperature-dependent capacitor comprises a first conductive plate, a second conductive plate located in a parallel-planar orientation to the first conductive plate, and a dielectric material located between the first conductive plate and the second conductive plate, the dielectric material having a temperature-dependent dielectric constant (?) value, wherein the temperature-dependent capacitor has a positive correlation of an operating temperature of the temperature-dependent capacitor to a capacitance value of the temperature-dependent capacitor.

Abstract: Provided is a preparation method of a detector material. The present disclosure epitaxially grows a buffer layer on a surface of a gallium arsenide substrate, deposits a silicon dioxide layer on the buffer layer, and etches the silicon dioxide layer on the buffer layer according to a strip pattern by photolithography and etching to form strip growth regions with continuous changes in width. Finally, a molecular beam epitaxy (MBE) technology is used to epitaxially grow the detector material in the strip growth regions under set epitaxy growth conditions. Because of the same mobility of atoms arriving at the surface of the substrate, numbers of atoms migrating to the strip growth regions are different due to different widths of the strip growth regions, such that compositions of the material change with the widths of the strip growth regions or a layer thickness changes with the widths of the strip growth regions.

Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain region in the cover semiconductor layer on first and second sides of the second channel region; first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.

Abstract: A manufacturing method of a SRAM memory device includes forming two transistors on a substrate, forming an inner dielectric layer covering the two transistors, forming contacts in the inner dielectric layer for coupling to source nodes of the two transistors, forming a metal interconnect structure on the inner dielectric layer, wherein a portion of an n-th metal layer of the metal interconnect structure is utilized as a lower metal layer, wherein n?1. An opening is formed in the metal interconnect structure to expose the lower metal layer, and then a capacitor is formed in the opening. The capacitor includes the lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer, and an upper metal layer from bottom to top. The upper metal layer is a portion of an m-th metal layer of the metal interconnect structure, wherein m?n+1.

Abstract: A display apparatus includes a substrate in which a plurality of pads are disposed, a plurality of micro LEDs, wherein each micro LED from among the plurality of micro LEDs is electrically connected to a respective group of pads from among the plurality of pads and mounted on the substrate, and a plurality of protrusion members, wherein each protrusion member from among the plurality of protrusion members protrudes from the substrate and is formed adjacent to a respective pad from among the plurality of pads.

Abstract: Provided are a capacitor and a semiconductor device including the capacitor. The capacitor includes a first electrode; a plurality of dielectric films on the first electrode in a sequential series, the plurality of dielectric layers having different conductances from each other; and a second electrode on the plurality of dielectric films, wherein the capacitor has a capacitance which converges to a capacitance of one of the plurality of dielectric films.

Abstract: A domain wall moving type magnetic recording element includes: a domain wall moving layer in which first layers containing a rare earth metal and second layers containing a transition metal are alternately stacked in a first direction; and a first electrode and a second electrode which face the domain wall moving layer and are arranged to be away from each other. The domain wall moving layer has SOT suppression parts which are positioned in one of interfaces between the first layers and the second layers and contain a non-magnetic metal. The SOT suppression parts are locally distributed at the interface.

Abstract: A display panel is provided. The display panel includes at least two first pixels, at least two second pixels, and at least two third pixels. An area of the first pixel, an area of the second pixel, and an area of the third pixel are inversely proportional to a luminous efficiency of a luminescent material of the first pixel, a luminous efficiency of a luminescent material of the second pixel, and a luminous efficiency of a luminescent material of the third pixel, respectively. The disclosure can avoid the drawback of color shift of the display panel.

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

Abstract: A method for chemical mechanical polishing includes receiving an angular removal profile for a carrier head and an angular thickness profile of a substrate. Prior to polishing the substrate, a desired angle of the carrier head relative to the substrate is selected for loading the substrate into the carrier head. Selecting the desired angle is performed based on a comparison of the angular removal profile for the carrier head and the angular thickness profile of the substrate to reduce angular non-uniformity in polishing. The carrier head is rotated to receive the substrate at the desired angle, the substrate is transferred to the carrier head and loaded in the carrier head with the carrier head at the desired angle relative to the substrate, and the substrate is polished.