Abstract: An apparatus and method for fabricating a backside contacted mosaic detector array which provides close detector packing in one or more directions by eliminating over the edge contacts typically used. The method uses indium or other coldweldable metal, both as a means for fastening the array from the backside to its circuit board and as a means for providing electrical contact with each detector.

Abstract: Light Emitting Diodes (LED) arrays are made by first applying LED monoliths to a metallic pallet, such as a copper pallet, and then securing the pallets to a substrate in a preferred geometrical arrangement. Because copper is so readily machinable, one is able to produce sizes as required for the geometry of an LED array and because of the rigidity, the problem of the fragile modules is removed since they are part of the pallets.

Abstract: In manufacturing a field effect transistor, a pattern which has a wider upper layer and a narrower lower layer is formed at a gate electrode position. Using the pattern as a mask, first and second impurity regions are formed on both the sides of a gate region by ion implantation. Subsequently, at least the lower layer is buried in a material, such as an organic high polymer material, having a selectivity in etching characteristics with respect to the pattern material. After removing the lower layer, an electrode material is embedded in the resulting hole so as to form a gate electrode.

Abstract: A self-registering method of manufacturing an air-(vacuum) -insulated crossing multilayer wiring system of large density is disclosed. Between the lowermost and uppermost wiring layers an intermediate layer is provided in which recesses are formed between the intermediate layer and the lowermost wiring layer. By means of said recesses the intermediate layer can be removed entirely at the area of the crossings during the etching process, while elsewhere portions of the intermediate layer remain as supporting parts or as connecting members.

Abstract: A process for fabricating a field effect transistors having a source electrode, a drain electrode and a gate electrode, including the steps of forming first to third conjoined narrow portions of thin film on an active region of a semiconductor, the second thin film portion having a different etching rate from the first and third and implanting ions into the active region to form a high carrier concentration region by using the conjoined films as a mask. The thickness of the second film portion determines the gate electrode length and the thickness of the third film portion determines the distance between the high carrier concentration region at the source side and the gate electrode.

Abstract: A stacked CMOS structure is disclosed which uses buried N++ source and drain for the non-self-aligned bulk N-channel driver devices together with an oversized polygate on which a non-self aligned P-channel load device is made from a second layer of poly or recrystallized poly. The non-self aligned pair of stacked devices provides increased density of devices per unit area with a simple process at the cost of increased gate to source and gate to drain parasitic capicitances.

Abstract: The present invention is directed to a process for providing overvoltage protection to a thyristor and to the thyristor so protected and comprises contacting the space charge region of the forward blocking junction of the thyristor with an electrical contact when the predetermined switching voltage is reached.

Abstract: In a semiconductor element using avalanche multiplication such as a light-receiving element or a microwave oscillating element, a semiconductor A and a semiconductor B which satisfy the following condition:X.sub.A <X.sub.B, X.sub.A +E.sub.gA <X.sub.B +E.sub.gBwhere X.sub.A is the electron affinity of the semiconductor A, E.sub.gA is the forbidden band width of the semiconductor A, X.sub.B is the electron affinity of the semiconductor B and E.sub.gB is the forbidden band width of the semiconductor B, are layered and an electric field is applied in parallelism to the layer, whereby an impact ionization coefficient rate is obtained by junction of the different kinds of semiconductors. At least one of the semiconductors A and B is composed of a mixed crystal comprising three or more elements, and the mole fraction of said one semiconductor is varied to thereby control the value of the impact ionization coefficient rate.

Abstract: A method of forming semiconductor devices wherein a continuous metallic sheet is cut under computer control into a personalized lead pattern. The pattern is then moved to a bonding station. A bonding tool actuated by computer control moves from one terminal end to another to sequentially bond terminals to the semiconductor device. A variety of various patterns and chips can be handled on the same line using common cutting and bonding tools. A second bond can be made from the lead pattern to either a lead frame or a substrate.

Abstract: An integrated circuit having active devices in electro-optical conversion material regions and single crystal silicon regions which are in a polycrystalline silicon support. The electro-optical conversion material regions are separated from the polycrystalline silicon by a containment layer. The method includes forming trenches in a wafer of electro-optical conversion material, covering the trenches with a containment layer and overfilling with polycrystalline silicon, removing material to expose polycrystalline silicon in the trenches and converting exposed portions of the polycrystalline silicon to single crystal silicon.

Abstract: An imaging device includes a wafer of single crystal semiconductor material having a first surface with an input surfacing region which extends into the wafer from the first surface and a second surface with a charge storage portion which includes a plurality of discrete charge storing regions which extend into the wafer of the second surface. The wafer includes a potential barrier within the input signal sensing portion for controlling blooming. The wafer is improved by including a passivation region within the input sensing portion for stabilizing the energy level of the conductivity band of the minority carriers at the Fermi energy level of the semiconductor wafer. Additionally, an electrical leakage reduction region extends into the wafer from the second surface. The leakage reduction region is contiguous with each of the discrete charge storage regions.

Abstract: All the layers of the anode foil of an electrolytic capacitor roll (5) are cold welded to a piece of tabbing (8) using radiussed weld tooling (10, 12, 13) which bends the foil layers in the course of the welding operation so as to enable a good weld to be effected. The cathode foil layers are welded to their piece of tabbing in the same way. Optionally the roll may be partially flattened at the time the welds are made.

Abstract: A method of forming a metallic silicide on silicon or polysilicon in which a masking layer such as silicon dioxide is formed on a silicon slice and patterned to expose selected areas of the slice surface. The slice is then sputter etched followed by in situ deposition of a metal layer. The slice is heated to convert the portion of the metal layer in contact with the silicon and/or polysilicon to a metal silicide, then the non-converted metal is removed by a selective etchant. According to another embodiment of the invention a titanium layer is deposited and reacted in an ambient including nitrogen to prevent the out-diffusion of silicon through the TiSi.sub.2 and titanium layers.

Abstract: The disclosure relates to a method manufacturing semiconductor devices which minimizes encroachment by utilizing a polycrystalline silicon (polysilicon) layer over a grown oxide on the substrate with a nitride layer positioned above the polysilicon layer. A patterned resist is then formed in the active device regions and the device is then etched in the regions where the resist has not been applied to remove the nitride layer, the polysilicon layer and the oxide layer in one embodiment and, in a second embodiment, also removes a portion of the substrate. The silicon substrate portion which is exposed is then oxidized by field oxidation to provide, in the first embodiment, an oxide layer which rises above the level of the polysilicon layer and, in the second embodiment, to a point equal to or slightly above the oxide layer beneath the polysilicon layer. The nitride and polysilicon layer are then stripped or, alternatively, the polysilicon layer can be oxidized.

Abstract: Small scale integrated chips are fabricated from a semiconductor wafer and subsequently pretested and formed into large area arrays with self aligning and self locking characteristics due to the axial orientation of the semiconductor wafer and geometries employed for the chips based upon the wafer orientation, whereby the spacing of abutting chip edges in an array may be less than 7 .mu.m. The chips are fabricated from <110> axial wafer, e.g., silicon <110> axial wafer, wherein the chip boundaries are aligned with vertical {111} planes of the crystalline material so that each of the chips formed from the wafer may be defined within parallelogrammatic like geometries defined by these planes and their intersections. The term "parallelogrammatic like geometries" means all geometric shapes capable of being formed with various vertical {111} planes within the crystalline structure of the wafer.

Abstract: A silicon substrate having a silicon dioxide bird's head is provided. A thermal oxide layer is grown on the exposed silicon surface. A layer, e.g., 4000 A.degree., of phosphogermanosilicate glass is deposited on the thermal oxide and on the silicon dioxide bird's head. The structure is heated to 950.degree. C., causing a reflow of the glass which results in a planar surface. The thermal oxide and the phosphogermanosilicate glass are then wet etched at the same rate with a solution of hydrofluoric acid, ammonium fluoride, and deionized water. The wet etch is terminated when the exposed silicon surface is reached, resulting in a smooth surface as defined by the planar reflow surface. Other embodiments are disclosed.

Abstract: For the manufacture of semiconductor wafers with a rear side having a geting action in subsequent oxidation processes by means of the action of light, especially laser, radiation ("laser damage"), there are advantageously chosen wafers with a fine surface structure that contains faces that are inclined by at least 15.degree. in the actual profile by comparison with the geometrically ideal profile of the surface according to known standards. As a result, in comparison to smooth surfaces, considerable savings in energy and time are achieved.

Abstract: Electrical contacts with low specific-contact resistance to In-based Group III-V compound semiconductors (e.g., p-InGaAsP) are formed by electron beam depositing a thin Pt layer directly on the semiconductor and sintering at about 450.degree.-525.degree. C. for about 5-30 minutes. Light emitting diodes without dark spot defects can be fabricated using this technique.

Abstract: A method of fabricating MESFET devices having a T-shaped gate electrode is disclosed. The method includes the formation of a single layer of resist material on a semiconductor surface; formation of a resist cavity through optical lithography, the cavity exposing a selected portion of the semiconductor surface; depositing by way of dual-angle evaporation gate walls within said resist cavity, the gate walls defining a T-shaped gate cavity; depositing gate electrode material within the gate cavity, removing the resist material, and removing the gate walls from the gate electrode material.

Abstract: A method of making improved step metal coverage of semiconductor device using enhanced reflow of phosphosilicate glass by ion implantation of arsenic at low temperature is provided. In one embodiment, the fabrication processing includes implanting arsenic into the phosphosilicate glass and reflowing the ion implanted phosphosilicate glass by heating the phosphosilicate glass to smooth the phosphosiliate glass for allowing a metal interconnection.