Abstract: Systems, apparatuses, and methods related to thermal leveling are described. Thermal leveling can be performed on a host computing system as opposed to on a memory system. Thermal leveling can include operations performed by a host to control temperature characteristics and/or power consumption of a memory system. For instance, a host computing system can control temperature characteristics of multiple memory devices that are deployed in a memory system. In an example, a set of processing resources (e.g., a thermal leveling component) can be provided on a host. The set of processing resources can receive information corresponding to thermal characteristics of a memory device coupled to the host and control a thermal setting for the memory device based on the received thermal characteristics.

Abstract: A system includes at least a secure-boot file, a hypervisor, and a host. The secure-boot file is configured to securely boot a VM, where the secure-boot file is signed with a boot private key. The hypervisor is configured to run the VM. The hypervisor includes a boot public key corresponding to the boot private key, such that the hypervisor is configured to validate the secure-boot file, and the hypervisor is signed with a hypervisor private key. A kernel of the host is configured to run the VM, where the kernel includes a hypervisor public key corresponding to the hypervisor private key, such that the host is configured to validate the hypervisor.

Abstract: A method includes: generating, based on a hash function using at least one input including first data, a first digest; storing the first data in a memory; reading the first data from the memory; generating, based on the read data, a second digest; comparing the first digest and the second digest; and determining, based on comparing the first digest and the second digest, whether the read data is corrupted.

Abstract: An information processing method includes, by an information processing device, acquiring a snapshot of data stored in a main storage device of the information processing device in a state where an external device is not authenticated yet, after the information processing device is powered ON; performing first authentication in which the information processing device authenticates the external device after the snapshot is stored in an auxiliary storage device of the information processing device; and performing second authentication in which the information processing device is started up using the snapshot and authenticates the external device after the information processing device is powered ON again.

Abstract: An information handling system includes a non-volatile dual in-line memory module (NVDIMM) and a processor. The NVDIMM instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated on the information handling system. The second partition is accessible to the operating system. The first partition includes a first region and a second region. The processor boots the information handling system to configure the NVDIMM based upon information from the first region, detects an error associated with the NVDIMM, and writes information associated with the error to the second region.

Abstract: A method of restoring an encrypted memory image in a system comprising volatile and non-volatile memory initiates a RESTORE of the image from the non-volatile memory to the volatile memory during a BIOS phase of a boot process for the system. If, during an operating system phase, it is determined that the RESTORE failed due to a password error, a password is written to the non-volatile memory and the BIOS phase of the boot process is reinitiated.

Abstract: A system with improved power performance for tasks executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a first core into a lower power state responsive to the first core waiting for a second core to complete a second task. In some embodiments long messages are subdivided to allow a receiving core to resume useful work sooner.

Abstract: A power supply for a synchronized appliance is disclosed and includes a first energy store having a first energy storage capacity, a processor powered by energy from the first energy store, and a second energy store having a second energy storage capacity greater than the first energy storage capacity. The processor initiates charging of the second energy store after a delay beginning at a time of receipt of a charge of predefined level from the first energy store.

Abstract: An integrated circuit may include multiple power consuming cores, multiple sets of power gates, and a control circuit. Each set of power gates can be configured to provide one or more power paths to provide power to a corresponding power consuming core. The control circuit can be configured to switch the set of power gates allocated to a power consuming core in a sequence of switching events during an activation period in response to one of the power consuming cores being turned on or off. The sequence of switching events may vary the number of power gates being switched or vary a time interval between the switching events.

Abstract: In some examples, an electronic device may determine a target time to which the remaining battery charge is to last, such as based on a user input or historical usage of the electronic device. Additionally, the electronic device may determine a current amount of the battery charge remaining, and may determine user activities likely to occur between the present time and the target time. Based at least partially on the amount of the battery charge remaining and the user activities determined to be likely to occur before the target time, the electronic device may apply one or more power management restrictions to one or more resources of the electronic device.

Abstract: In disclosed techniques, secure communication initiation and execution is used for datacenter power control. Information relating to power control is encrypted for inclusion in a first data payload. The first data payload is used for datacenter power infrastructure control. The first data payload is sent from a first component within a datacenter to a second component within the datacenter. The first component and the second component enable power infrastructure power control of the datacenter. The datacenter power infrastructure control is modified based on decryption of the first data payload by the second component within the datacenter. The first data payload provides for intelligent power control within the datacenter. Modifying the datacenter power infrastructure control dynamically changes power control within the datacenter. The changing power control changes power policies within the datacenter. The first component is authenticated using the first data payload. Encryption includes obscurity.

Abstract: Various embodiments provide a voltage regulator circuit including two or more discontinuous conduction mode (DCM) phases coupled to an output node and coupled in parallel with one another. A control circuit may detect a trigger and switch all of the two or more DCM phases to a first state (charge state) responsive to the detection. The control circuit may switch a first DCM phase, of the two or more DCM phases, to a second state (discharge state) after a first predetermined time period in the first state and may switch a second DCM phase, of the two or more DCM phases, to the second state after a second predetermined time period in the first state, wherein the second predetermined time period is different than the first predetermined time period. Other embodiments may be described and claimed.

Abstract: An apparatus is described. The apparatus includes a power management integrated circuit (PMIC) semiconductor chip having logic circuitry to implement a PMIC/PMIC interface having a downstream signal line and an upstream signal line. The downstream signal line to communicate any of multiple states that a downstream PMIC semiconductor chip is to implement with one of multiple voltage levels, where, different ones of the multiple voltage levels correspond to different ones of the multiple states. The upstream signal line is to communicate whether or not the downstream PMIC semiconductor chip is ready to receive a next one of the multiple voltage levels.

Abstract: In one example implementation according to an embodiment described herein, a computer-implemented method includes detecting input/output (I/O) interrupts for executing I/O operations occurring over a period of time. The method further includes calculating an I/O interrupt delay time (IIDT) for each I/O interrupt occurring during the period of time. The method further includes binning the IIDT for each I/O interrupt occurring during the period of time into one of a plurality of bins based on a value of the IIDT, each of the plurality of bins storing a count of IIDT values within a defined range. The method further includes determining a highest IIDT value. The method further includes identifying a performance degradation based at least on one of the count of IIDT values of each of the plurality of bins or the highest IIDT value. The method further includes implementing a corrective action to mitigate the performance degradation.

Abstract: Architectures or techniques are presented that can facilitate automatic recovery from a component failure exhibited by a building automation system (BAS) control device and/or a heating, ventilation, and air conditioning (HVAC) control device. A failure or fault condition with a software or firmware component can be automatically repaired. A failure or fault condition with a hardware component can be identified, potentially more quickly, and hardware component replacement can be streamlined or simplified.

Abstract: In an embodiment, an operating point controller for two or more circuit regions in an integrated circuit is discussed. The OPC is configured to both i) set a resource state, including operating voltage and operating frequency, for each of those circuit regions, and ii) identify events to initiate transitions between two or more operating points for a given circuit region. The operating point controller is also configured to manage transitions between operating points for the two or more circuit regions on the integrated circuit. The operating point controller is a hardware based machine implemented in logic rather than software operating on a CPU processor.

Abstract: An integrated circuit and method are provided for managing power domains. The integrated circuit has first circuitry provided within a first power domain, and a distributed power controller for controlling transition of the first power domain between a plurality of power states. The distributed power controller comprises at least power control circuitry in a second power domain and additional power control circuitry in a third power domain. Whilst the current power state of the first power domain is in any one of at least two of the plurality of power states, the second power domain is allowed to be placed in a power saving state where the power control circuitry loses knowledge of the current power state of the first power domain. However, the third power domain is prevented from entering that power saving state.

Abstract: In an embodiment, the OPC manages at least one of i) gating state and ii) different operating frequencies for a given circuit region. The operating point controller is configured to be capable of both 1) having sole control to set and manage the gating state and operating frequency for the given circuit region based on a first set of events, as well as 2) delegating control to a local power domain controller to set and manage i) gating state for components in that circuit region, ii) different operating frequencies for components in that circuit region, and iii) combinations of both, based on a second set of events, on a per operating point basis. The multiple operating points for that circuit region have different operating voltage levels and operating frequencies, and when delegated, the local power domain controller will chose the gating state and/or operating frequency.

Abstract: In one embodiment, the present disclosure includes a method of reducing power in an artificial intelligence processor. For each cycle, over a plurality of cycles, an AI model is translated into operations executable on an artificial intelligence processor. The translating is based on power parameters that correspond to power consumption and performance of the artificial intelligence processor. The AI processor is configured with the executable operations, and input activation data sets are processed. Accordingly, result sets, power consumption data, and performance data are generated and stored over the plurality of cycles. The method further includes training an AI algorithm using the stored parameters, the power consumption data, and the performance data. A trained AI algorithm outputs a plurality of optimized parameters to reduce power consumption of the AI processor. The AI model is then translated into optimized executable operations based on the plurality of optimized parameters.

Abstract: A cascaded clock ring network includes a clock path that transmits a source clock through series-connected processing nodes, from a first processing node to a last processing node. A data path transmits data through the processing nodes in response to the transmitted source clock, from the first processing node to the last processing node. The last processing node provides the transmitted source clock as an end clock signal, and provides the transmitted data as end data values. The end data values are written into a FIFO memory in response to the end clock signal. The end data values are subsequently read from the FIFO memory using the source clock signal, and are provided to the first processing node. A synchronizing circuit ensures that a plurality of end data values are initially written into the FIFO memory before an end data value is read from the FIFO memory.