Abstract: A semiconductor structure includes a substrate, a conductive feature over the substrate, a dielectric layer over the conductive feature and the substrate, and a structure disposed over and electrically connected to the conductive feature. The structure is partially surrounded by the dielectric layer and includes a first metal-containing layer and a second metal-contain layer surrounded by the first metal-containing layer. The first and the second metal-containing layers include different materials. A lower portion of the first metal-containing layer includes a transition metal or a transition metal nitride and an upper portion of the first metal-containing layer includes a transition metal fluoride or a transition metal chloride.

Abstract: A display device comprises a substrate, a semiconductor layer thereon, a first insulating layer on the semiconductor layer, a first conductive layer on the first insulating layer and including a first electrode pattern, a second insulating layer on the first insulating layer and including first and second conductive patterns, a third insulating layer on the second conductive layer, and a display element layer on the third insulating layer and including a first pixel electrode connected to the first conductive pattern through a first via hole, a second pixel electrode connected to the second conductive pattern through a second via hole, and a micro light-emitting element between the pixel electrodes, the first conductive pattern contacting the semiconductor layer through a first contact hole and the first electrode pattern through a second contact hole, and the second conductive pattern overlapping the first electrode pattern to form a first capacitor therewith.

Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.

Abstract: A thermal processing system for performing thermal processing can include a workpiece support plate configured to support a workpiece and heat source(s) configured to heat the workpiece. The thermal processing system can include window(s) having transparent region(s) that are transparent to electromagnetic radiation within a measurement wavelength range and opaque region(s) that are opaque to electromagnetic radiation within a portion of the measurement wavelength range. A temperature measurement system can include a plurality of infrared emitters configured to emit infrared radiation and a plurality of infrared sensors configured to measure infrared radiation within the measurement wavelength range where the transparent region(s) are at least partially within a field of view the infrared sensors.

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a device layer, a first interconnect layer, and a first bonding layer. The device layer includes a processor and a logic circuit, and the first bonding layer includes a first bonding contact. The semiconductor device also includes a second semiconductor structure including an array of static random-access memory (SRAM) cells, a second interconnect layer, and a second bonding layer including a second bonding contact. The first bonding contact is in contact with the second bonding contact. The processor is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer.

Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1X feature and at least one wider than 1X feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1X feature and at least one wider than 1X feature; the first metal material is reflowed such that the at least one 1X feature is filled with the first metal material and the at least one wider than 1X feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1X feature is filled with the second metal material.

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

Abstract: A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.

Abstract: A second BEOL layer including a via dielectric layer surrounding a via including an upper metal stud and a lower metal stud separated by a liner, and a magnetic tunnel junction (MTJ) stack aligned above the via. A first back end of line (BEOL) layer including a BEOL dielectric layer surrounding a BEOL metal layer, a second BEOL layer including a via dielectric layer surrounding a via including an upper metal stud and a lower metal stud separated by a liner, a magnetic tunnel junction (MTJ) stack aligned above the via. Forming a via dielectric layer as a second back end of line (BEOL) layer, an opening, a lower metal stud in the opening, a liner on the lower metal stud and on exposed side surfaces of the opening, an upper metal stud in remaining portions of the opening, and forming a magnetic tunnel junction (MTJ) stack aligned above.

Abstract: A monitoring device for monitoring a fabrication process in a fabrication system. The monitored fabrication system includes a process chamber and a plurality of flow components. A quartz crystal microbalance (QCM) sensor monitors one flow component of the plurality of flow components of the fabrication system and is configured for exposure to a process chemistry in the one flow component during the fabrication process. A controller measures resonance frequency shifts of the QCM sensor due to interactions between the QCM sensor and the process chemistry in the one flow component during the fabrication process. The controller determines a parameter of the fabrication process in the process chamber as a function of the measured resonance frequency shifts of the QCM sensor within the one flow component.

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

Abstract: A single crystal semiconductor includes a strain compensation layer; an amorphous substrate disposed on the strain compensation layer; a lattice matching layer disposed on the amorphous substrate and including two or more single crystal layers; and a single crystal semiconductor layer disposed on the lattice matching layer, the lattice matching layer including a direction control film disposed on the amorphous substrate and including a single crystal structure, and a buffer layer including a material different from that of the direction control film, the buffer layer being disposed on the direction control film and including a single crystal structure.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Abstract: A highly-sensitive ultrasonic transducer with good yield is provided. The ultrasonic transducer includes a cavity layer, a pair of electrodes positioned above and below the cavity layer, insulating layers disposed above and below each of the pair of electrodes, and a filled hole that penetrates, in a vertical direction, at least a portion of the insulating layers positioned above the cavity layer. When the ultrasonic transducer is viewed from above, each electrode of the pair of electrodes includes, at a position that overlaps the embedded hole, a non-electrode region where the electrodes are not formed.

Abstract: A method of transferring multiple semiconductor devices from a first substrate to a second substrate comprises the steps of forming the multiple semiconductor devices adhered on the first substrate, wherein the multiple semiconductor devices comprises a first semiconductor device and a second semiconductor device, and the first semiconductor device and the second semiconductor device have a first gap between thereof; separating the first semiconductor device and the second semiconductor device from the first substrate; sticking the first semiconductor device and the second semiconductor device to a surface of the second substrate, wherein the first semiconductor device and the second semiconductor device have a second gap between thereof; wherein the first gap and the second gap are different.

Abstract: According to an embodiment, an etching method includes forming a first layer on a substrate having a main surface including first and second regions adjacent to each other, the first layer including a portion covering the first region and having a plurality of openings or one or more openings defining a plurality of island-shaped portions, and the first layer further including a portion as a continuous layer covering the second region, forming a catalyst layer an a portion(s) of the main surface exposed in the openings by plating, forming a second layer to cover a portion of the catalyst layer adjacent to a boundary between the first and second regions and expose a portion of the catalyst layer spaced apart from the boundary, and etching the substrate in a presence of the catalyst layer and the second layer.

Abstract: The invention relates to a method for forming a porous portion in a substrate, an implantation of ions in at least one region of a layer, for example based on a semiconductor material, so as to form a portion enriched with at least one gas in the implanted region, and then a laser annealing of the nanosecond type so as to form a porous portion. The use of the ion implantation makes it possible to dissociate the deposition of the layer based on semiconductor material from the incorporation of gas. A great variety of porous structures can be obtained by the method. These porous structures can be adapted for numerous applications according to the properties sought.

Abstract: A manufacturing apparatus and a manufacturing method are provided. A manufacturing apparatus includes a chamber, and a stage disposed in the chamber. The stage includes an upper surface on which a target substrate is disposed, a lower surface opposite to the upper surface, a first side surface extending between the upper surface and the lower surface in a first direction, and a second side surface extending between the upper surface and the lower surface in a second direction perpendicular to the first direction. The first side surface is in a round shape, and at least a portion of the first side surface is convex toward an outside of the stage.

Abstract: A substrate processing apparatus includes a processing tub configured to store therein a processing liquid in which multiple substrates are to be immersed; multiple liquid supplies each of which includes a supply line through which the processing liquid is supplied to an inside of a water tank of the processing tub and a heating device configured to heat the processing liquid at a portion of the supply line; and multiple in-tank temperature sensors configured to measure a temperature of the processing liquid at multiple positions within the water tank of the processing tub.