Patents Examined by Alexander G. Ghyka
  • Patent number: 12225787
    Abstract: A display device includes a substrate including a display area and a pad area, a transistor including an active layer disposed in the display area, a gate electrode disposed on the active layer, and a source electrode and a drain electrode disposed on the gate electrode, a fan-out line disposed in the pad area, an auxiliary line disposed on the fan-out line, a first interlayer insulating layer disposed between the gate electrode and the source electrode and between the fan-out line and the auxiliary line, and a first organic layer disposed between the first interlayer insulating layer and the auxiliary line, wherein the first organic layer does not overlap the display area.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: February 11, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gyung Min Baek, Tae Wook Kang, Shin Il Choi
  • Patent number: 12218286
    Abstract: A light emitting module including a circuit board, a plurality of unit pixels arranged on the circuit board, a molding member covering the unit pixels, and an anti-glare layer disposed on the molding member, in which the molding member includes a first molding layer at least partially covering each of the unit pixels, and a second molding layer covering the first molding layer.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: February 4, 2025
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Jae Hyun Park, Seung Sik Hong
  • Patent number: 12218188
    Abstract: A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: February 4, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Ye Shao, John K Arch
  • Patent number: 12217960
    Abstract: Semiconductor devices and methods of manufacture are provided whereby fences are formed over a substrate and III-V materials are grown over the substrate, wherein the fences block growth of the III-V materials. As such, smaller areas of the III-V materials are grown, thereby preventing stresses that occur with the growth of larger sheets.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min-Sung Kuo, I-Kai Hung, Po-Wei Chen, Chung-Cheng Chen
  • Patent number: 12211789
    Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: January 28, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chenming Hu, Shu-Jui Chang, Chen-Han Chou, Yen-Teng Ho, Chia-Hsing Wu, Kai-Yu Peng, Cheng-Hung Shen
  • Patent number: 12211905
    Abstract: A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure comprises a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: January 28, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Patent number: 12205903
    Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Jhih-Yu Wang, Yu-Hsiang Hu
  • Patent number: 12205944
    Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: January 21, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Akram A. Salman, Binghua Hu
  • Patent number: 12205854
    Abstract: The present disclosure provides an electronic device including a redistribution layer, a plurality of passive components, and an electronic component. The redistribution layer includes a first insulating layer, a second insulating layer, and a plurality of traces electrically connected to each other through a first opening of the first insulating layer and a second opening of the second insulating layer, wherein the first insulating layer has a first side away from the second insulating layer, and the second insulating layer has a second side away from the first insulating layer. The passive components are disposed on the first side. The electronic component is disposed on the second side. The plurality of passive components are electrically connected to the electronic component through the plurality of traces.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: January 21, 2025
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Kuang-Chiang Huang, Yu-Ting Liu, Yi-Hung Lin, Cheng-En Cheng
  • Patent number: 12205847
    Abstract: A method of removing a substrate from III-nitride based semiconductor layers with a cleaving technique. A growth restrict mask is formed on or above a substrate, and one or more III-nitride based semiconductor layers are grown on or above the substrate using the growth restrict mask. The III-nitride based semiconductor layers are bonded to a support substrate or film, and the III-nitride based semiconductor layers are removed from the substrate using a cleaving technique on a surface of the substrate. Stress may be applied to the III-nitride based semiconductor layers, due to differences in thermal expansion between the III-nitride substrate and the support substrate or film bonded to the III-nitride based semiconductor layers, before the III-nitride based semiconductor layers are removed from the substrate. Once removed, the substrate can be recycled, resulting in cost savings for device fabrication.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: January 21, 2025
    Assignee: The Regents of the University of California
    Inventors: Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li
  • Patent number: 12199209
    Abstract: Described herein is an optical sensor, a detector including the optical sensor for an optical detection of at least one object, a method for manufacturing the optical sensor and various uses of the optical detector. The optical sensor can be supplied as a non-bulky hermetic package which provides an increased degree of protection against possible degradation by humidity and/or oxygen over long terms. Further, the optical sensor may be easily manufactured and integrated on a circuit carrier device.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: January 14, 2025
    Assignee: TRINAMIX GMBH
    Inventors: Wilfried Hermes, Sebastian Valouch, Sebastian Mueller, Regina Hoeh, Heidi Bechtel, Timo Altenbeck, Fabian Dittmann, Bertram Feuerstein, Thomas Hupfauer, Anke Handreck, Robert Gust, Robert Send, Ingmar Bruder
  • Patent number: 12199036
    Abstract: The present disclosure describes an interconnect structure and a method forming the same. The interconnect structure can include a substrate, a layer of conductive material over the substrate, a metallic capping layer over the layer of conductive material, a layer of insulating material over top and side surfaces of the metallic capping layer, and a layer of trench conductor formed in the layer of insulating material and the metallic capping layer.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jason Huang, Liang-Chor Chung, Cheng-Yuan Li
  • Patent number: 12198990
    Abstract: A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of separating, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a through hole formed by separating the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the through hole.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: January 14, 2025
    Assignee: DISCO CORPORATION
    Inventors: Youngsuk Kim, Byeongdeck Jang, Akihito Kawai, Shunsuke Teranishi
  • Patent number: 12191326
    Abstract: A solid-state imaging device according to an embodiment of the present disclosure includes a stacked photoelectric converter for each of pixels. The stacked photoelectric converter has a plurality of photoelectric conversion elements stacked therein. The plurality of photoelectric conversion elements each has different wavelength selectivity. This solid-state imaging device further includes a plurality of data output lines from which pixel signals based on electric charges outputted from the photoelectric conversion elements are outputted. A plurality of data output lines is provided for each predetermined unit pixel column. The plurality of the data output lines is equal in number to an integer multiple of the photoelectric conversion elements stacked in the stacked photoelectric converter.
    Type: Grant
    Filed: October 6, 2023
    Date of Patent: January 7, 2025
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Toshiaki Ono
  • Patent number: 12191143
    Abstract: A plasma enhanced chemical vapor deposition (PECVD) method includes loading a wafer having a magnetic layer thereon into a processing chamber equipped with a radio frequency (RF) system, introducing an aromatic hydrocarbon precursor into the processing chamber, and turning on an RF source of the RF system to decompose the aromatic hydrocarbon precursor into active radicals at a frequency greater than about 1000 Hz to form a graphene layer over the magnetic layer.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: January 7, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jian-Zhi Huang, Yun-Hsuan Hsu, I-Chih Ni, Chih-I Wu
  • Patent number: 12191138
    Abstract: A processing method of a workpiece with a circular disc shape includes sticking a tape to one surface of the workpiece and integrating the workpiece and a frame through the tape, holding the workpiece by a holding unit with the interposition of the tape, and irradiating the other surface of the workpiece located on the opposite side to the one surface with a pulsed laser beam having such a wavelength as to be absorbed by the workpiece from the side of the other surface. In irradiating the laser beam, the other surface is annularly irradiated with the laser beam in the state in which the orientation of the laser beam is adjusted in such a manner that the laser beam has an angle of incidence formed due to inclination with respect to a normal to the other surface of the workpiece by a predetermined angle.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: January 7, 2025
    Assignee: DISCO CORPORATION
    Inventors: Toshio Tsuchiya, Toshiyuki Yoshikawa, Tomoyuki Hongo
  • Patent number: 12165879
    Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method for manufacturing a semiconductor structure includes: forming a conductive layer, a protective layer, and a mask layer in sequence on the substrate, the mask layer including a first pattern facing the first region and a second pattern facing the second region; forming a restriction pattern located in the second region by etching the protective layer using the mask layer as a mask; and forming contact pads located in the first region and connecting wires located in the second region on the conductive layer by etching the conductive layer using the mask layer as a mask.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xinman Cao, Jun Xia, Zhongming Liu, Shijie Bai
  • Patent number: 12156427
    Abstract: A display device may improve an aperture ratio. The display device comprises a substrate provided with transmissive areas and a plurality of subpixels disposed between the transmissive areas, a driving transistor provided in each of the plurality of subpixels, an anode electrode provided in each of the plurality of subpixels and coupled with the driving transistor through an anode contact hole, a bank overlapped with at least a portion of the anode contact hole over the anode electrode, a light emitting layer provided over the anode electrode and the bank, and a cathode electrode provided over the light emitting layer. An end of at least one side of the anode electrode is exposed without being covered by the bank.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: November 26, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: MoonSoo Kim, DoYoung Kum
  • Patent number: 12148629
    Abstract: Describes are shutter disks comprising one or more of titanium (Ti), barium (Ba), or cerium (Ce) for physical vapor deposition (PVD) that allows pasting to minimize outgassing and control defects during etching of a substrate. The shutter disks incorporate getter materials that are highly selective to reactive gas molecules, including O2, CO, CO2, and water.
    Type: Grant
    Filed: November 21, 2023
    Date of Patent: November 19, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Kang Zhang, Junqi Wei, Yueh Sheng Ow, Kelvin Boh, Yuichi Wada, Ananthkrishna Jupudi, Sarath Babu
  • Patent number: 12148622
    Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu