Patents Examined by Alexander G. Ghyka
  • Patent number: 11232948
    Abstract: The present disclosure provides systems and methods for a layered substrate. A layered substrate may include a core comprising graphite. The layered substrate may also include a coating layer comprising a coating material that surrounds the core, wherein the coating material has a melting point that is greater than a melting point of silicon.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy
  • Patent number: 11232943
    Abstract: A method includes receiving a structure having a substrate, a conductive feature over the substrate, and a dielectric layer over the conductive feature. The method further includes forming a hole in the dielectric layer to expose the conductive feature; forming a first metal-containing layer on sidewalls of the hole; and forming a second metal-containing layer in the hole and surrounded by the first metal-containing layer. The first and the second metal-containing layers include different materials. The method further includes applying a first chemical to recess the dielectric layer, resulting in a top portion of the first and the second metal-containing layers protruding above the dielectric layer; and applying a second chemical having fluorine or chlorine to the top portion of the first metal-containing layer to convert the top portion of the first metal-containing layer into a metal fluoride or a metal chloride.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: January 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Shang Hsiao, Chun Hsiung Tsai, Clement Hsingjen Wann
  • Patent number: 11227795
    Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11227765
    Abstract: The invention provides a quantum dot manufacturing method and related quantum dot semiconductor structure. The quantum dot semiconductor structure includes: a conductive ridge on a substrate; an insulative layer covering the substrate and the conductive ridge, wherein the insulative layer includes a top portion and two sidewalls over the conductive ridge; a plurality of quantum dots respectively embedded within a plurality of silicon dioxide spacer islands, which are adhered to the sidewalls of the insulative layer; and a plurality of conductive ledges adhered to the silicon dioxide spacer islands, wherein each of the conductive ledges is a portion of an electrode with alignment to the corresponding quantum dot.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: January 18, 2022
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Pei-Wen Li, Kang-Ping Peng, Ching-Lun Chen, Tsung-Lin Huang
  • Patent number: 11222782
    Abstract: A method for fabricating a silicon carbide semiconductor device includes providing a SiC epitaxial layer disposed over a surface of a SiC substrate, forming an implant aperture in a hardmask layer on a surface of the expitaxial SiC layer, implanting contact and well regions in the SiC epitaxial layer through the hardmask layer, the contact region lying completely within and recessed from edges of the well region by performing one of implanting the well region through the implant aperture, reducing the area of the implant aperture forming a reduced-area contact implant aperture and implanting the contact region through the reduced-area implant aperture to form a contact region, and implanting the contact region through the implant aperture, increasing the area of the implant aperture to form a increased-area well implant aperture and implanting the well region through the increased-area implant aperture to form a well region completely surrounding the contact region.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: January 11, 2022
    Assignee: Microchip Technology Inc.
    Inventors: Amaury Gendron-Hansen, Bruce Odekirk
  • Patent number: 11217457
    Abstract: A method of fabricating a semiconductor device including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe lane region, sequentially stacking a mold layer and a supporting layer on the substrate, forming a first mask layer on the supporting layer, the first mask layer including a first stepped region on the wafer edge region, forming a step-difference compensation pattern on the first stepped region, forming a second mask pattern including openings, on the first mask layer and the step-difference compensation pattern, and sequentially etching the first mask layer, the supporting layer, and the mold layer using the second mask pattern as an etch mask to form a plurality of holes in at least the mold layer may be provided.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: January 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungjin Kim, Byung-Hyun Lee, Yoonyoung Choi, Tae-Kyu Kim, Heesook Cheon, Bo-Wo Choi, Hyun-Sil Hong
  • Patent number: 11217605
    Abstract: The first gate insulating film is an insulating film made of silicon oxide, and to which hafnium (Hf) is added without addition of aluminum (Al). Also, the second gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added without addition of hafnium. The third gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added. Further, the fourth gate insulating film is an insulating film made of silicon oxide, and to which hafnium is added. Accordingly, it is possible to reduce the power consumption of the semiconductor device.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: January 4, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shibun Tsuda
  • Patent number: 11211246
    Abstract: A method for selectively modifying a base material surface, includes applying a composition on a surface of a base material to form a coating film. The coating film is heated. The base material includes a surface layer which includes a first region including silicon. The composition includes a first polymer and a solvent. The first polymer includes at an end of a main chain or a side chain thereof, a group including a first functional group capable of forming a bond with the silicon. The first region preferably contains a silicon oxide, a silicon nitride, or a silicon oxynitride. The base material preferably further includes a second region that is other than the first region and that contains a metal; and the method preferably further includes, after the heating, removing with a rinse agent a portion formed on the second region, of the coating film.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: December 28, 2021
    Assignee: JSR CORPORATION
    Inventors: Hiroyuki Komatsu, Tomohiro Oda, Hitoshi Osaki, Masafumi Hori, Takehiko Naruoka
  • Patent number: 11211522
    Abstract: A method of transferring semiconductor devices from a first substrate to a second substrate, including providing the semiconductor devices which are between the first substrate and the second substrate. The semiconductor devices include a first semiconductor device and a second semiconductor device, and the first semiconductor device and the second semiconductor device have a first gap between thereof. The first semiconductor device and the second semiconductor device are moved from the first substrate by a picking unit. The picking unit, the first semiconductor device, and the second semiconductor device are moved close to the second substrate. The picking unit has a space apart from the second substrate. The first semiconductor device and the second semiconductor device are transferred from the picking unit to the second substrate. The he first semiconductor device and the second semiconductor device on the second substrate have a second gap between thereof. The first gap and the second gap are different.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: December 28, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Hao-Min Ku, You-Hsien Chang, Shih-I Chen, Fu-Chun Tsai, Hsin-Chih Chiu
  • Patent number: 11201157
    Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a processor and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of static random-access memory (SRAM) cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: December 14, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Jun Liu
  • Patent number: 11195716
    Abstract: The method of producing a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions containing carbon, phosphorus, and hydrogen as constituent elements to form a modified layer that is located in a surface layer portion of the semiconductor wafer and that contains the constituent elements of the cluster ions as a solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer. The ratio y/x of the number y of the phosphorus atoms with respect to the number x of the carbon atoms satisfies 0.5 or more and 2.0 or less, where the number of atoms of carbon, phosphorus, and hydrogen in the cluster ions is expressed by CxPyHz (x, y, and z are integers each equal to or more than 1).
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 7, 2021
    Assignee: SUMCO CORPORATION
    Inventor: Ryosuke Okuyama
  • Patent number: 11195722
    Abstract: Methods for wet-etching semiconductor samples and devices fabricated from the same are disclosed. The methods can be for selectively wet-etching a semiconductor sample comprising selecting a liquid-phase solution such that when the semiconductor sample is etched with the liquid-phase solution, at least a portion of one of a first doped region or a second doped region is etched at a greater rate than at least a portion of the other of the first doped region or the second doped region; and wet-etching, with the liquid-phase solution, the at least a portion of one of the first doped region or the second doped region at a first etch rate and the at least a portion of the other of the first doped region or the second doped region at a second etch rate; wherein the first etch rate can be greater than the second etch rate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: December 7, 2021
    Assignee: Georgia Tech Research Corporation
    Inventors: Shyh-Chiang Shen, Theeradetch DetchProhm, Russell Dean Dupuis, Young Jae Park, Oliver Moreno
  • Patent number: 11189586
    Abstract: A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The semiconductor chip is disposed on a first substrate electrode, and one end of a Cu wire is bonded onto the Ag fired cap by means of an ultrasonic wave. There is provided a semiconductor device capable of improving a power cycle capability, and a fabrication method of such a semiconductor device.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 30, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Takukazu Otsuka
  • Patent number: 11189487
    Abstract: A high-pressure dielectric film curing apparatus, such as a high-pressure batch furnace, is controlled to an elevated cure temperature and super-atmospheric pressure for the duration of the film curing time with the cure pressure achieved at least partially with a vapor of aqueous ammonia in fluid communication with the chamber. The cure temperature may vary, for example between 175° C., and 400° C., or more. The cure pressure may also vary as limited by the saturated water vapor pressure, for example between 100 PSIA and 300 PSIA, or more. The aqueous ammonia may be injected into the chamber or vaporized upstream of the chamber. One or more carrier and/or diluent gas (vapor) may be introduced into the chamber to adjust the partial pressure of ammonia vapor, water vapor, and the diluent.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Jonathan E. Leonard, Aravind S. Killampalli, Chad Byers, Jay P. Gupta
  • Patent number: 11183488
    Abstract: Embodiments of three-dimensional (3D) memory devices with stacked device chips using interposers and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device is disclosed. An alternating conductor/dielectric stack is formed at a first side of a chip substrate. A memory string extending vertically through the alternating conductor/dielectric stack is formed. A chip contact is formed at a second side opposite to the first side of the chip substrate and is electrically connected to the memory string. A first interposer contact is formed at a first side of an interposer substrate. A second interposer contact is formed at a second side opposite to the first side of the interposer substrate and is electrically connected to the first interposer contact through the interposer substrate. The first interposer contact is attached to the chip contact.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: November 23, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jun Liu, Li Hong Xiao
  • Patent number: 11177156
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor wafer having an active side and a back side opposite to the active side is provided. A plurality of conductive bumps are provided on the active side. A protection film is laminated on the active side, wherein the protection film includes a dielectric film covering the plurality of conductive bumps and a cover film covering the dielectric film. A thinning process is performed on the back side to form a thinned semiconductor wafer. The cover film is removed from the dielectric film. A singularization process is performed on the thinned semiconductor wafer with the dielectric film to form a plurality of semiconductor devices.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
  • Patent number: 11171286
    Abstract: There is provided a method of processing a workpiece for manufacturing a magnetoresistive effect element, the workpiece including a first multilayer film and a second multilayer film, the first multilayer film including a first magnetic layer, a second magnetic layer and a tunnel barrier layer formed between the first magnetic layer and the second magnetic layer, and the second multilayer film constituting a pinning layer in the magnetoresistive effect element. The method includes etching the first multilayer film and the second multilayer film, and heating the workpiece after the etching or during the etching. The heating includes heating the workpiece while adjusting an ambient condition of the workpiece.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: November 9, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takuya Kubo, Song yun Kang
  • Patent number: 11171054
    Abstract: A method is presented for forming a fully aligned via (FAV) structure. The method includes depositing a first dielectric adjacent a conductive material, forming a surface aligned monolayer (SAM) over the conductive material, the SAM defining a long chain SAM formed by a layer-by-layer growth technique, depositing a second dielectric over the SAM and the first dielectric, performing chemical mechanical polishing (CMP) to planarize the second dielectric, and etching the SAM to form the FAV structure.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Son Nguyen, Rudy J. Wojtecki, Noel Arellano, Alexander Edward Hess, Thomas Jasper Haigh, Jr., Cornelius Brown Peethala, Balasubramanian S. Pranatharthi Haran
  • Patent number: 11171017
    Abstract: Describes are shutter disks comprising one or more of titanium (Ti), barium (Ba), or cerium (Ce) for physical vapor deposition (PVD) that allows pasting to minimize outgassing and control defects during etching of a substrate. The shutter disks incorporate getter materials that are highly selective to reactive gas molecules, including O2, CO, CO2, and water.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: November 9, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Zhang Kang, Junqi Wei, Yueh Sheng Ow, Kelvin Boh, Yuichi Wada, Ananthkrishna Jupudi, Sarath Babu
  • Patent number: 11171166
    Abstract: The present disclosure provides a camera assembly and a packaging method thereof, a lens module, and an electronic device.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 9, 2021
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Da Chen, Mengbin Liu