Abstract: A packaged module for use in a wireless communication device has a substrate supporting a crystal and a first die that includes at least a microprocessor and one or more of radio frequency transmitter circuitry and radio frequency receiver circuitry. The first die is disposed between the crystal and the substrate. An overmold encloses the first die and the crystal. The substrate also supports a second die that includes at least a power amplifier for amplifying a radio frequency input signal, where the second die is disposed on an opposite side of the substrate from the first die and the crystal.

Abstract: A circuit device includes a first conductive plate and a second conductive plate each having a belt-shaped portion arranged side-by-side with each other, a third conductive plate having a belt-shaped portion is arranged side-by-side with and spaced apart from the other side portion of the first conductive plate, a first circuit component having a first terminal connected to the first conductive plate and a second terminal connected to the second conductive plate, a second circuit component having a first terminal connected to the first conductive plate and a second terminal connected to the third conductive plate, a first external connection portion provided at the belt-shaped portion of the first conductive plate, and a second external connection portion provided at the belt-shaped portion of the second conductive plate or a third external connection portion provided at the belt-shaped portion of the third conductive plate.

Abstract: Provided is a cooler having high cooling efficiency and low pressure loss of fluid. A cooler includes: a flow-channel part at least including a plate-like fin (top plate) and a plate-like fin (bottom plate); and a continuous groove-like flow channel defined between the top plate and the bottom plate to flow fluid, the cooler being configured to cool semiconductor elements. When the flow-channel part is viewed from the direction parallel to the top plate and intersecting the flow channel, the flow channel has a corrugated shape so that a face of the flow channel closer to the top plate and a face of the flow channel closer to the bottom plate bend in a synchronized manner toward the top plate and the bottom plate.

Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.

Abstract: A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias.

Abstract: A method for manufacturing a semiconductor device package includes: accommodating a substrate in a cavity in a center of a carrier substrate having the cavity in which a substrate with a semiconductor chip mounted thereon is accommodated in the center, having a support portion in contact with a side wall of the cavity to form an upper surface of the side wall and surrounding the cavity, and formed of a light-transmitting material; defining a molding portion of the substrate by pressing the support portion and an edge region of the substrate; and molding the molding portion, to cover the semiconductor chip.

Abstract: An optically readable chip ID is provided to an imprintable material that is formed as a last level of an integrated circuit (IC) chip using nanoimprint lithography. The nanoimprint lithography process provides an array of indentations into the imprintable material that is typically arranged in a hexadecimal pattern. The hexadecimal pattern includes one or more optically readable characters which combine to encode chip location identification data. The chip location identification data identifies a unique location of the product chip on a wafer prior to dicing.

Abstract: A power module includes a substrate having a first layer and a second layer which are connected to one another and arranged above one another. The first layer includes a first dielectric material having a metallization arranged on a side facing the second layer and the second layer includes a second dielectric material having a metallization arranged on a side facing away from the metallization of the first dielectric material. A power semiconductor having a first contact area and a second contact area opposite the first contact area is connected to the metallization of the first dielectric material via the first contact area and arranged in a first recess of the second layer. A metallic first encapsulation encapsulates the power semiconductor in a fluid-tight manner, with the second contact area of the power semiconductor being electrically conductively connected to the metallization of the second dielectric material via the first encapsulation.

Abstract: A method for producing an electric circuit in which a contact carrier comprising a first contact area and a second contact area is provided. An insulating body is applied to the circuit carrier and at least partially covers the first contact area and the second contact area. The insulating body comprises cut-outs in regions both contact areas. A flowable electrical conducting medium is introduced into the insulating body.

Abstract: A power electronic module (1) including at least one semiconductor (5) that is connected to connection conductors (6, 7), and including a dielectric carrier (10) having both a fixed layer (9), on which at least one of said connection conductors (6) is mounted, and a movable layer (11), the fixed layer (9) and the movable layer (11) exhibiting similar dielectric permittivities and being superposed along at least one surface facing the at least one connection conductor (6).

Abstract: Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.

Abstract: A method includes bonding a plurality of dies to a substrate. A first die of the plurality of dies is larger than a second die of the plurality of dies. The method includes adhering a first stress relief structure to the substrate. A distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance. The method includes adhering a second stress relief structure to the substrate. A distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance. The first stress relief structure is discontinuous with respect to the second stress relief structure.

Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.

Abstract: A 3D integrated circuit, the circuit including: a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; where the second wafer is bonded face-to-face on top of the first wafer, where the bonded includes copper to copper bonding; and where the second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.

Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Abstract: A semiconductor device includes a semiconductor wafer having one or more suspended nanosheet extending between first and second source/drain regions. A gate structure wraps around the nanosheet stack to define a channel region located between the source/drain regions. The semiconductor device further includes a first all-around source/drain contact formed in the first source/drain region and a second all-around source/drain contact formed in the second source/drain region. The first and second all-around source/drain contacts each include a source/drain epitaxy structure and an electrically conductive external portion that encapsulates the source/drain epitaxy structure.

Abstract: A semiconductor package includes a semiconductor chip, an encapsulant, and an interconnection member. The semiconductor chip has connection pads. The encapsulant encapsulates a portion of the semiconductor chip. The interconnection member includes a first insulating layer disposed on the encapsulant and a portion of the semiconductor chip, a redistribution layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and the redistribution layer. The redistribution layer is electrically connected to the connection pads of the semiconductor chip, and a thickness of the second insulating layer is greater than a thickness of the first insulating layer.

Abstract: First semiconductor devices, a first dielectric material layer, a porous dielectric material layer, and a metal interconnect structure formed within a second dielectric material layer are formed on a front-side surface of a first semiconductor substrate. A via cavity extending through the first semiconductor substrate and the first dielectric material layer are formed. The via cavity stops on the porous dielectric material layer. A continuous network of pores that are free of any solid material therein continuously extends from a bottom of the via cavity to a surface of the metal interconnect structure. A through-substrate via structure is formed in the via cavity. The through-substrate via structure includes a porous metallic material portion filling the continuous network of pores and contacting surface portions of the metal interconnect structure. Etch damage to the first semiconductor devices and metallic particle generation may be minimized by using the porous metallic material portion.

Abstract: A semiconductor device includes a substrate, a semiconductor device module, and a heat conductor. The semiconductor device module is on the substrate. The semiconductor device module includes an interposer substrate, one or more semiconductor device chips, a covering resin, and a metal film. The one or more semiconductor device chips are on a first surface of the interposer substrate. The covering resin is in contact with the first surface of the interposer substrate and the one or more semiconductor device chips and encloses the one or more semiconductor device chips. The metal film is in contact with the covering resin and covers the covering resin. The heat conductor is in thermal contact with the substrate and the metal film, and has a higher thermal conductivity than the covering resin.

Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.