Patents Examined by Alexander Oscar Williams
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Patent number: 10032806Abstract: A display device includes a substrate including a first planarization region and a second planarization region inclined at a predetermined angle with respect to the first planarization region. A display device further includes a first wiring disposed in the second planarization region. A display device additionally includes a flexible film bonded with the substrate in the first planarization region and the second planarization region and connected to the first wiring in the second planarization region.Type: GrantFiled: February 3, 2017Date of Patent: July 24, 2018Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Tae An Seo, Jin Hwan Choi, Tae Woong Kim, Bo Ik Park, Ju Chan Park
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Patent number: 10032643Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.Type: GrantFiled: December 22, 2014Date of Patent: July 24, 2018Assignee: Intel CorporationInventors: Jasmeet S. Chawla, Ruth A. Brain, Richard E. Schenker, Kanwal Jit Singh, Alan M. Myers
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Patent number: 10026709Abstract: An anisotropic electrically conductive film has a structure wherein the electrically conductive particles are disposed on or near the surface of an electrically insulating adhesive base layer, or a structure wherein an electrically insulating adhesive base layer and an electrically insulating adhesive cover layer are laminated together and the electrically conductive particles are disposed near the interface therebetween. Electrically conductive particle groups configured from two or more electrically conductive particles are disposed in a lattice point region of a planar lattice pattern. A preferred lattice point region is a circle centered on a lattice point. A radius of the circle is not less than two times and not more than seven times the average particle diameter of the electrically conductive particles.Type: GrantFiled: November 17, 2015Date of Patent: July 17, 2018Assignee: DEXERIALS CORPORATIONInventor: Yasushi Akutsu
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Patent number: 10026717Abstract: Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.Type: GrantFiled: February 13, 2017Date of Patent: July 17, 2018Assignee: Invensas CorporationInventors: Cyprian Emeka Uzoh, Rajesh Katkar
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Patent number: 10023775Abstract: Provided is a film adhesive which is preferably used as a NCF, void-free, has excellent electrical connectivity and its high reliability, does not develop cracks easily, and has high surface flatness. Also provided is a semiconductor device in which the film adhesive according to the present invention is used as an NCF during the manufacture of the semiconductor device. The film adhesive according to the present invention contains (A) an epoxy resin; (B) a bisphenol F type phenoxy resin; (C) a phenol resin-based curing agent; (D) a modified imidazole compound; (E) a silica filler; (F) oxyquinoline; and (G) a butadiene-acrylonitrile-methacrylic acid copolymer. The content of component (A) is 19.3 to 33.8 parts by mass. The content of component (B) is 7.5 to 9.1 parts by mass. The content of component (D) is 1.915 to 5 parts by mass. The content of component (E) is 30 to 60 parts by mass. The content of component (F) is 2.5 to 10 parts by mass.Type: GrantFiled: January 12, 2016Date of Patent: July 17, 2018Assignee: NAMICS CorporationInventors: Satomi Kawamoto, Yoshihide Fukuhara, Hiromi Saito, Atsushi Saito, Toyokazu Hotchi
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Patent number: 10008488Abstract: In one embodiment, the semiconductor module includes a module substrate and a first substrate mounted on and electrically connected to a first surface of the module substrate. The first substrate has one or more first electrical connectors of the semiconductor module, and the first substrate electrically connecting the first electrical connector to the module substrate.Type: GrantFiled: April 17, 2017Date of Patent: June 26, 2018Assignee: Samsung Electronics Co., Inc.Inventors: Yongkwan Lee, Kundae Yeom, Jongho Lee, Hogeon Song
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Patent number: 10002853Abstract: A semiconductor package includes a substrate, and a first semiconductor chip stack disposed on the substrate. The first semiconductor chip stack includes a plurality of first semiconductor chips. The first semiconductor chips are stacked in a staircase configuration along a first direction. A first support is disposed on the substrate. The first support is spaced apart from the first semiconductor chip stack. A second semiconductor chip stack is disposed on the first semiconductor chip stack and the first support. The second semiconductor chip stack includes a plurality of second semiconductor chips. The second semiconductor chips are stacked in a second staircase configuration along a second direction opposite the first direction. A height of the first semiconductor chip stack is substantially equal to a height of the first support.Type: GrantFiled: February 3, 2017Date of Patent: June 19, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Joo Young Oh
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Patent number: 9997487Abstract: A display device includes: a first substrate; a wire portion disposed on the first substrate; a pad portion connected with the wire portion; a printed circuit board facing the first substrate and including an output electrode; and an anisotropic conductive film disposed between the first substrate and the printed circuit board, wherein the anisotropic conductive film comprises a plurality of conductive particles disposed with a constant gap, and the plurality of conductive particles respectively disposed at apexes of virtual regular hexagons in a plan view, with a longest diagonal of the respective virtual regular hexagon being parallel with the y-axis.Type: GrantFiled: February 3, 2017Date of Patent: June 12, 2018Assignee: Samsung Display Co., Ltd.Inventors: Kyeong Yeol Heo, Joon Sam Kim, Ji Hoon Kim
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Patent number: 9997428Abstract: An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a substrate, pluralities of vias disposed in the substrate. The vias are disposed in a hexagonal arrangement.Type: GrantFiled: July 14, 2015Date of Patent: June 12, 2018Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Marshall Maple, Ashish Alawani, Li Sun, Sarah Haney
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Patent number: 9997430Abstract: A heat dissipation structure of a semiconductor device with excellent heat dissipation applicable to surface-mount thin semiconductor devices is provided, and preferably a heat dissipation structure of a semiconductor device also with excellent insulating reliability is provided. In a heat dissipation structure 101 of a semiconductor device 10, the semiconductor device 10 has an electric bonding surface 11a electrically connected with a substrate 20 and a heat dissipation surface 11b on an opposite side thereof, wherein the heat dissipation surface 11b is bonded or contacted to a heat spreader 31 via a non-insulated member 32, and the heat spreader 31 is bonded or contacted to a heat sink 30 via an insulated member 41.Type: GrantFiled: January 20, 2017Date of Patent: June 12, 2018Assignee: OMRON CorporationInventor: Eiichi Omura
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Patent number: 9980369Abstract: A mounting board includes: a first electronic component that includes first solder balls, one of the first solder balls being surrounded by at least three of the first solder balls; a first capacitor that includes a first power supply terminal and a first ground terminal; a second electronic component that includes second solder balls, each of the second solder balls not being surrounded by at least three of the second solder balls; and a second capacitor that includes a second power supply terminal and a second ground terminal. A distance from the first ground terminal to the first electronic component is less than or equal to a distance from the first power supply terminal to the first electronic component. A distance from the second power supply terminal to the second electronic component is less than or equal to a distance from the second ground terminal to the second electronic component.Type: GrantFiled: June 22, 2017Date of Patent: May 22, 2018Assignee: JOLED INC.Inventor: Shunsuke Itakura
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Patent number: 9960123Abstract: The present invention provides a method of forming a semiconductor structure. A wafer with a dicing region is provided, the dicing region comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. Next, an aligning mark is formed in the dicing region, wherein the aligning mark is a mirror symmetrical pattern and comprises a plurality of second patterns in the middle region and a plurality of third patterns in the third region, each third pattern has a plurality of lines and the lines comprises a plurality of inner lines which are formed by a sidewall image transfer (SIT) process.Type: GrantFiled: April 13, 2017Date of Patent: May 1, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ying-Chiao Wang, Yu-Hsiang Hung, Chao-Hung Lin, Ssu-I Fu, Chih-Kai Hsu, Jyh-Shyang Jenq
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Patent number: 9953939Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.Type: GrantFiled: November 18, 2016Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Liang Lin, Yu-Jen Tseng, Chang-Chia Huang, Tin-Hao Kuo, Chen-Shien Chen
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Patent number: 9953960Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.Type: GrantFiled: April 10, 2017Date of Patent: April 24, 2018Assignee: ChipMOS Technologies Inc.Inventor: Shih-Wen Chou
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Patent number: 9947752Abstract: A semiconductor device may include a semiconductor substrate, a first metal film covering a surface of the semiconductor substrate; a protection film covering a peripheral portion of a surface of the first metal film; and a second metal film covering a range extending across a center portion of the surface of the first metal film and a surface of the protection film, wherein a recess may be provided in the surface of the protection film, and a part of the second metal film may be in contact with an inner surface of the recess.Type: GrantFiled: May 22, 2017Date of Patent: April 17, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Akitaka Soeno
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Patent number: 9941236Abstract: To prevent cracks of an interlayer insulation film at the time of wire bonding while maintaining adhesion of an aluminum pad electrode and the interlayer insulation film in a semiconductor device in which the aluminum pad electrode and a lead frame are connected with bonding wire by a ball bonding technology. In a bonding pad that is configured to have multiple pad electrodes each with two or more layers, the pad electrodes being electrically connected with one another through vias, the vias are not arranged under an area to which a capillary end of a wire bonder contacts at the time of the wire bonding.Type: GrantFiled: August 24, 2016Date of Patent: April 10, 2018Assignee: Renesas Electronics CorporationInventor: Tadahiro Miwatashi
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Patent number: 9922922Abstract: A microchip includes a passivation layer formed over underlying circuitry, a redistribution layer formed over the passivation layer, and a cap layer formed over the redistribution conductors of the redistribution layer and in contact with the passivation layer. The passivation layer and the cap layer have one or more compatibilities that provide sufficient adhesion between those two layers to prevent metal migration from the conductors of the redistribution layer between the interfaces of the passivation and cap layers. In one embodiment, the passivation and cap layers are each formed from an inorganic oxide (e.g., SiO2) using a process (e.g., PECVD) that provides substantially-uniform step coverage by the cap layer in trench and via regions of underlying circuitry. The invention increases the reliability of the microchip, because it eliminates metal migration, and the electrical shorting caused therefrom, in the redistribution layer.Type: GrantFiled: September 16, 2016Date of Patent: March 20, 2018Assignee: OmniVision Technologies, Inc.Inventors: Chi-Kuei Lee, Ying Chung, Ying-Chih Kuo, Wei-Feng Lin
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Patent number: 9922964Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate, and a device die formed over the substrate. The device die has a first height. The package structure includes a dummy die formed over the substrate and adjacent to the device die, and the dummy die has a second height. The second height is smaller than the first height. The package structure also includes a package layer formed between the device die and the dummy die.Type: GrantFiled: September 19, 2016Date of Patent: March 20, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Wei Chen, Li-Hsien Huang
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Patent number: 9922940Abstract: A semiconductor device includes a substrate, and interconnects provided above the substrate. The device further includes a first insulator that is provided on the interconnects and on air gaps provided between the interconnects, surrounds the interconnects from lateral sides of the interconnects, and is formed of a first insulating material. The device further includes a second insulator that surrounds an interconnect region including the interconnects and the air gaps from the lateral sides of the interconnects through the first insulator, includes no portion provided between the interconnects, and is formed of a second insulating material different from the first insulating material.Type: GrantFiled: August 22, 2016Date of Patent: March 20, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takashi Watanabe, Takeshi Arakawa
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Patent number: 9917070Abstract: A method for arranging electronic components that includes a plurality of electronic components pasted onto a first front face of a carrier having a bonding layer. The front face and/or the electronic components being provided with a plurality of bonding points and the diameter of and distance between the bonding points are selected such that each of the plurality of electronic components is attached by at least three bonding points to the carrier having the bonding layer. The method also includes arranging at least one portion of the plurality of the components on a switching element carrier and connecting the components to the carrier. The method also includes detaching a component from the carrier having a bonding layer, using a solvent or a mechanical force that separates the carrier having a bonding layer and the switching element carrier from one another.Type: GrantFiled: January 28, 2015Date of Patent: March 13, 2018Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.Inventors: Hans-Hermann Oppermann, Kai Zoschke, Lena Goullon