Patents Examined by Alexander Sofocleous
  • Patent number: 9679652
    Abstract: A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method comprises: obtaining an erased state voltage of a first memory cell and a programmed state voltage of the first memory cell, where the first memory cell is operated in a first programming mode; and operating the first memory cell in a second programming mode if a width of a gap between the erased state voltage and the programmed state voltage is larger than a first threshold value. Accordingly, the reliability of the first memory cell may be improved.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: June 13, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Patent number: 9646708
    Abstract: An input/output interface circuit is provided for a memory device. The input/output interface circuit receives a first control signal and a second control signal, and provides an output clock signal. The input/output interface circuit includes a plurality of circuit blocks coupled in series, the a plurality of circuit blocks including an input terminal coupled to the first control signal and the second control signal, and an output terminal providing the output clock signal, a plurality of power switch transistors, each power switch transistor including a control terminal and coupled between a corresponding one of the circuit blocks and a power supply terminal, and a plurality of switch control circuits, each switch control circuit coupled to the control terminal of a corresponding one of the power switch transistors. The switch control circuits are configured to activate the circuit blocks in a first predetermined order and deactivate the circuit blocks in a second predetermined order.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: May 9, 2017
    Assignee: SanDisk Technologies LLC
    Inventor: Hitoshi Miwa
  • Patent number: 9576621
    Abstract: A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: February 21, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anand Seshadri, Dharin Shah, Parvinder Rana, Wah Kit Loh
  • Patent number: 9558832
    Abstract: To maintain constant an output voltage of a boosted voltage circuit even when a program current of a nonvolatile memory increases; in a boosted voltage circuit provided in a semiconductor device, an output voltage of a charge pump is detected by a voltage dividing circuit, and on-off control is performed on an oscillation circuit for driving the charge pump so that the detected output voltage becomes constant. Further, an output current of the charge pump is detected, and a control current according to a magnitude of the detected output current is generated. The control current is fed into or drawn from a coupling node between a plurality of series-coupled resistance elements configuring the voltage dividing circuit.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuaki Katou
  • Patent number: 9548115
    Abstract: This variable resistance element is provided with a variable resistance film, a first electrode, which is disposed in contact with one surface of the variable resistance film, and a second electrode, which is disposed in contact with the other surface of the variable resistance film. The first and the second electrodes have corner portions, respectively, and the distance between the corner portions of the first and the second electrodes is set equal to the shortest distance between the first and the second electrodes. Furthermore, the variable resistance element has a third electrode, which is disposed on the one surface of the variable resistance film.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 17, 2017
    Assignee: NEC CORPORATION
    Inventors: Munehiro Tada, Toshitsugu Sakamoto, Makoto Miyamura
  • Patent number: 9548125
    Abstract: A semiconductor device and a method of operating the same are provided. The method includes determining whether a read operation on a selected page is a beginning read operation on the selected page; performing a least significant bit (LSB) read operation on the selected page when the read operation is the beginning read operation on the selected page according to a determination result, and performing a first sub-read operation on the selected page according to a result of the LSB read operation; and performing a second sub-read operation including the LSB read operation or a most significant bit (MSB) read operation on the selected page according to stored program state data when the read operation is not the beginning read operation on the selected page according to the determination result.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: January 17, 2017
    Assignee: SK Hynix Inc.
    Inventor: Byoung Young Kim
  • Patent number: 9535614
    Abstract: A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory maintenance queue based on priority) to correspond with threshold values of the parameters for a more efficient scheduling of memory maintenance. For example, at a low temperature threshold, only high priority maintenance operations are performed, while at a higher temperature threshold, any priority maintenance operation is performed.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: January 3, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Gautham Reddy, Nian Niles Yang, Alexandra Bauche
  • Patent number: 9536926
    Abstract: Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel junction antifuses by connecting said magnetic tunnel junction serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, John K. Debrosse, Chandrasekharan Kothandaraman
  • Patent number: 9514832
    Abstract: An access apparatus for memory card and a control method thereof are provided. The access apparatus is adapted for receiving a memory card with a side having a supply voltage pin and includes a slot module. The slot module includes a slot having a first side and a second side corresponding to each other. The first side and the second side are respectively configured with a first supply voltage pin and a second supply voltage pin, and the first supply voltage pin and the second supply voltage pin are spaced apart and opposite to each other. The access apparatus selectively determines whether to forbid performing a write operation to the memory card according to a conduction status of the first supply voltage pin and the second supply voltage pin with the supply voltage pin caused by a facing direction of the memory card inserted in the slot.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: December 6, 2016
    Assignee: Wistron Corporation
    Inventors: Qi Cao, Peng-Fei Li
  • Patent number: 9502109
    Abstract: Provided is a non-volatile semiconductor memory device capable of reliably preventing a malfunction of a read transistor without increasing the number of bit lines. In a non-volatile semi conductor memory device (1), program transistors (5a, 5b) and erase transistors (3a, 3b) serving as charge transfer paths during data programming and erasure are provided while a second bit line (BLN1) connected to the program transistor (5a) in a first cell (2a) for performing data programming also serves as a reading bit line in the other second cell (2b) by switching switch transistors (SWa, SWb) so that malfunctions of read transistors (4a, 4b) that occur because the read transistors are used for data programming and erasure can be reliably prevented without the number of bit lines being increased.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 22, 2016
    Assignee: FLOADIA CORPORATION
    Inventors: Yasuhiro Taniguchi, Hideo Kasai, Yutaka Shinagawa, Kosuke Okuyama
  • Patent number: 9496025
    Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
  • Patent number: 9496039
    Abstract: A storage device includes a flash memory and a buffer memory. A method of controlling interrupts includes: receiving data to be written to the storage device from an information processing device; writing the received data to be written to the storage device to the buffer memory; fetching the data in the buffer memory and writing the data to the flash memory; in which, after writing the received data to be written to the storage device to the buffer memory, if the amount of data in the buffer memory is less than the predetermined threshold, then sending a message indicating the completion of the write operation to the information processing device.
    Type: Grant
    Filed: June 15, 2013
    Date of Patent: November 15, 2016
    Assignee: MEMBLAZE TECHNOLOGY (BEIJING) CO., LTD.
    Inventors: Xuebing Yin, Yilei Wang
  • Patent number: 9478307
    Abstract: A memory device includes a memory cell which has one cell selection section and a storage section which is connected in series with respect to the cell selection section and which is selected as an access target for writing or reading by the cell selection section, in which the storage section is provided with a plurality of memory elements which are able to be written one time only and where information is held by changing resistance values in a non-written state and a written state.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: October 25, 2016
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Yuki Yanagisawa
  • Patent number: 9467050
    Abstract: A semiconductor apparatus includes a voltage supply circuit suitable for outputting a high voltage, a transfer circuit coupled between the voltage supply circuit and a peripheral circuit and suitable for transferring the high voltage to the peripheral circuit and a transfer control circuit suitable for outputting a transfer control signal to the transfer circuit to control the transfer of the high voltage to the peripheral circuit, wherein the transfer control circuit outputs the transfer control signal having a first positive voltage level to a gate of a transistor included in the transfer circuit when the voltage supply circuit outputs the high voltage to the transfer circuit.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: October 11, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yeonghun Lee, Hyun Heo, Min Gyu Koo, Dong Hwan Lee
  • Patent number: 9460779
    Abstract: A memory sensing method is provided. The memory sensing method comprises the following steps: sensing a first memory unit to obtain a first sensing result; sensing a second memory unit to obtain a second sensing result; and looking up a one-time sensing table according to the first and second sensing results to obtain an output data.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: October 4, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kin-Chu Ho, Hsiang-Pang Li
  • Patent number: 9447767
    Abstract: Aspects of the invention are directed to a single chip igniter such that it is possible to realize a reduction in operating voltage, an increase in noise tolerance, a reduction in size, and a reduction in cost. By reducing the gate threshold voltage of a MOS transistor, and reducing the operating voltages of a current limiter circuit, an overheat detector circuit, a timer circuit, an overvoltage protection circuit, an input hysteresis circuit, and the like, it is possible to reduce the operating voltage of a single chip igniter. In some aspects of the invention, the effective gate voltage of the MOS transistor is 1V or more, and the channel length of the MOS transistor is 4 ?m or less. Also, in some aspects of the invention, the thickness of a gate oxide film of the MOS transistor is 5 nm or more, 25 nm or less.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: September 20, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Kenichi Ishii
  • Patent number: 9437289
    Abstract: Provided an electronic device including a semiconductor memory unit. The semiconductor memory unit includes: a plurality of storage cells each including a variable resistance element of which resistance is changed in response to a current flowing across the variable resistance element and a selecting element coupled to one end of the variable resistance element; a plurality of word lines corresponding to the respective storage cells and each coupled to a selecting element of a corresponding storage cell; a first line coupled to one ends of the plurality of storage cells; a second line coupled to the other ends of the plurality of storage cells; a voltage adjuster configured to adjust the voltage levels of back bias voltages of the selecting elements of the plurality of storage cells; and an access control unit electrically coupled to the first and second lines and passing an access current to a selected storage cell among the plurality of storage cells.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: September 6, 2016
    Assignee: SK hynix Inc.
    Inventors: Byoung-Chan Oh, Yoon-Jae Shin
  • Patent number: 9437329
    Abstract: A semiconductor device includes: a first block, which is initialized during an initialization mode; and a second block, which is initialized while the first block latches first signals during a boot-up mode. Herein, the second block may latch second signals after being initialized during the boot-up mode.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: September 6, 2016
    Assignee: SK Hynix Inc.
    Inventor: Ga-Ram Park
  • Patent number: 9431072
    Abstract: A trimmable sense amplifier for use in a memory device is disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 30, 2016
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Yao Zhou, Xiaozhou Qian
  • Patent number: 9401192
    Abstract: A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level of a word line connected to each of the memory cells. The time determination signal generation circuit is configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined, and the timing circuit is configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: July 26, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masaki Okuda, Keizo Morita, Tomohisa Hirayama