Abstract: Apparatus, systems, and methods for write operations in spin transfer torque (STT) memory are described. In one embodiment, a memory comprises at least one spin-transfer torque (STT) memory device, temperature sensor proximate the STT memory device and a controller comprising logic, at least partially including hardware logic, to monitor an output of the temperature sensor, implement a first write operation protocol when the output of the temperature sensor fails to exceed a threshold temperature, and implement a second write operation protocol when the output of the temperature sensor exceeds the threshold temperature. Other embodiments are also disclosed and claimed.

Abstract: First and second read requests are received. First data is fetched in response to the first read request. The fetched first data is then stored. The fetched first data corresponds to an address of the first read request. The fetched first data is returned in response to the second read request.

Abstract: A solid state drive (SSD) with improved power efficiency includes one or more non-volatile memory devices configured to operate according to a programming voltage for a program function or an erase function and to a supply voltage for a read function. The SSD also includes a voltage regulator, external of the one or more non-volatile memory devices, having an output connected to the one or more non-volatile memory devices to supply the programming voltage and an input connected to receive a first voltage, the voltage regulator configured to convert the first voltage to the programming voltage. A discrete capacitor is connected to supply the first voltage to the voltage regulator. The one or more non-volatile memory devices operate according to the programming voltage supplied by the voltage regulator during both the normal operation of the SSD and in the event of a power loss or failure of the SSD.

Abstract: A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.

Abstract: Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. One example of the conductive region is a common source line that includes one or more local source lines and one or more global source lines. If the leakage current were to become high enough, the electrical short between the conductive region and the block select line could cause a plane level failure. If the leakage current is less than an amount that would cause a plane failure, but that indicates that the non-volatile memory device is susceptible to a plane failure, data may be moved out of the plane before the plane failure occurs. Thus, data loss may be prevented.

Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.

Abstract: Techniques are provided for reducing program disturb and short term data retention loss. Program disturb becomes worse for the drain-side memory cells at higher temperatures, while data retention generally does not become worse at higher temperatures. In one aspect, a deeper erase is provided for drain-side memory cells when the temperature is relatively high, to reduce program disturb. In another aspect, the verify levels of the programmed data states are lowered to reduce data retention loss when the temperature is relatively high. In another aspect, the number of read errors is used to adjust the depth of the depth of the erase operation. In another aspect, a pass voltage of a drain-side cell is lowered during a verify test for another cell to account for the deep erase of the drain-side cell.

Abstract: Approaches for a circuit are provided. The circuit includes a sense amplifier circuit which includes a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit, and the latching circuit which includes a primary driver actively driven by the first output data line true signal and a secondary driver actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line.

Abstract: Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the pre-amplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell.

Abstract: A memory array with RAM and embedded ROM including multiple RAM cells, a ROM cell, and a ROM enable circuit. Each RAM cell has a RAM cell structure with a first and second power terminals and configured to operate as a RAM cell when the memory array is in a RAM mode. The ROM cell has the same RAM cell structure in which at least one transistor is modified to cause the ROM cell to have a predetermined logic state. The ROM enable circuit enables bit lines of the ROM cell to control supply voltages provided to the power terminals of the RAM cells so that they settle to predetermined logic states in a ROM mode. The modified transistor has a pseudo transistor structure having a modified substrate that operates as a resistance, such as a doping region in the substrate having the same polarity type as the substrate.

Abstract: A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method comprises: obtaining an erased state voltage of a first memory cell and a programmed state voltage of the first memory cell, where the first memory cell is operated in a first programming mode; and operating the first memory cell in a second programming mode if a width of a gap between the erased state voltage and the programmed state voltage is larger than a first threshold value. Accordingly, the reliability of the first memory cell may be improved.

Abstract: An input/output interface circuit is provided for a memory device. The input/output interface circuit receives a first control signal and a second control signal, and provides an output clock signal. The input/output interface circuit includes a plurality of circuit blocks coupled in series, the a plurality of circuit blocks including an input terminal coupled to the first control signal and the second control signal, and an output terminal providing the output clock signal, a plurality of power switch transistors, each power switch transistor including a control terminal and coupled between a corresponding one of the circuit blocks and a power supply terminal, and a plurality of switch control circuits, each switch control circuit coupled to the control terminal of a corresponding one of the power switch transistors. The switch control circuits are configured to activate the circuit blocks in a first predetermined order and deactivate the circuit blocks in a second predetermined order.

Abstract: A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.

Abstract: To maintain constant an output voltage of a boosted voltage circuit even when a program current of a nonvolatile memory increases; in a boosted voltage circuit provided in a semiconductor device, an output voltage of a charge pump is detected by a voltage dividing circuit, and on-off control is performed on an oscillation circuit for driving the charge pump so that the detected output voltage becomes constant. Further, an output current of the charge pump is detected, and a control current according to a magnitude of the detected output current is generated. The control current is fed into or drawn from a coupling node between a plurality of series-coupled resistance elements configuring the voltage dividing circuit.

Abstract: This variable resistance element is provided with a variable resistance film, a first electrode, which is disposed in contact with one surface of the variable resistance film, and a second electrode, which is disposed in contact with the other surface of the variable resistance film. The first and the second electrodes have corner portions, respectively, and the distance between the corner portions of the first and the second electrodes is set equal to the shortest distance between the first and the second electrodes. Furthermore, the variable resistance element has a third electrode, which is disposed on the one surface of the variable resistance film.

Abstract: A semiconductor device and a method of operating the same are provided. The method includes determining whether a read operation on a selected page is a beginning read operation on the selected page; performing a least significant bit (LSB) read operation on the selected page when the read operation is the beginning read operation on the selected page according to a determination result, and performing a first sub-read operation on the selected page according to a result of the LSB read operation; and performing a second sub-read operation including the LSB read operation or a most significant bit (MSB) read operation on the selected page according to stored program state data when the read operation is not the beginning read operation on the selected page according to the determination result.

Abstract: A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory maintenance queue based on priority) to correspond with threshold values of the parameters for a more efficient scheduling of memory maintenance. For example, at a low temperature threshold, only high priority maintenance operations are performed, while at a higher temperature threshold, any priority maintenance operation is performed.

Abstract: Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel junction antifuses by connecting said magnetic tunnel junction serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage.

Abstract: An access apparatus for memory card and a control method thereof are provided. The access apparatus is adapted for receiving a memory card with a side having a supply voltage pin and includes a slot module. The slot module includes a slot having a first side and a second side corresponding to each other. The first side and the second side are respectively configured with a first supply voltage pin and a second supply voltage pin, and the first supply voltage pin and the second supply voltage pin are spaced apart and opposite to each other. The access apparatus selectively determines whether to forbid performing a write operation to the memory card according to a conduction status of the first supply voltage pin and the second supply voltage pin with the supply voltage pin caused by a facing direction of the memory card inserted in the slot.

Abstract: Provided is a non-volatile semiconductor memory device capable of reliably preventing a malfunction of a read transistor without increasing the number of bit lines. In a non-volatile semi conductor memory device (1), program transistors (5a, 5b) and erase transistors (3a, 3b) serving as charge transfer paths during data programming and erasure are provided while a second bit line (BLN1) connected to the program transistor (5a) in a first cell (2a) for performing data programming also serves as a reading bit line in the other second cell (2b) by switching switch transistors (SWa, SWb) so that malfunctions of read transistors (4a, 4b) that occur because the read transistors are used for data programming and erasure can be reliably prevented without the number of bit lines being increased.