Patents Examined by Alford W. Kindred
  • Patent number: 10424030
    Abstract: A system and computer implemented method for estimating difficulty of a document includes retrieving a subject document from a storage, setting difficulty of each keyword included in the subject document to locality of the keyword in the subject document as an initial value, estimating, by a processor, difficulty of each subject document by a statistical processing of the difficulties of keywords included in the subject document, and updating the difficulty of each keyword based on the difficulty of each subject document depending on a significance value of the keyword in the subject document.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yohei Ikawa, Shoko Suzuki
  • Patent number: 10417060
    Abstract: A computer system may include a processor configured to search storage locations for candidate Application Programming Interface (API) files that are to be published on an Internet of Things (IoT) platform configured to interact with IoT devices for different device manufacturers. The processor may generate a list of candidate APIs based on searching the storage locations; generate a list of published platform APIs published on the IoT platform; compare the list of candidate APIs with the list of published platform APIs; generate an API create list based on the comparing; generate an API update list based on the comparing; create one or more candidate APIs from the generated API create list on a testing system; and update one or more candidate APIs from the generated API update list on the testing system.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: September 17, 2019
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Tirth Nikhil Mona Shah, Lin Zhu
  • Patent number: 10360239
    Abstract: An automated system for defining a star schema for a data source. The system based on automatically gathered information from the data source such as entities and columns, entity column types and lengths, entity keys, relationships between and within entities, measures, workflow and correlated attributes, specialized entities, an update frequency of entities and columns, and grouping of entity and column updates associated with the source database automatically determines facts, dimensions, dimension hierarchies, measures, workflow specific measures (if data source has workflows) and workflow correlated attribute specific measures (if data source has temporal, priority, ownership and progress tracking attributes) to come up with a star schema for the data source.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: July 23, 2019
    Assignee: Numerify, Inc.
    Inventors: Rahul Kapoor, Gaurav Rewari, Renu Chintalapati, Aravind Sridharan, Ravishankar Muniasamy, Florian Schouten, David Shenk, Srinivas M. Vedagiri
  • Patent number: 10324965
    Abstract: A technique for suggesting patterns to search documents for information of interest includes acquiring a working set of spans for a document set that includes one or more documents. A list of one or more suggested patterns is generated by applying a pattern suggestion algorithm (PSA) to the set of spans for each document in the document set. One or more unique patterns are generated by applying a pattern consolidation algorithm (PCA) to the generated list of suggested patterns. Pattern information for each of the unique patterns is then generated. The pattern information includes a respective first count that corresponds to the number of times each of the unique patterns occurs in the document set.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Dimple Bhatia, Armageddon R. Brown, Yunyao Li, Margaret Zagelow
  • Patent number: 10303684
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are provided for resource scoring adjustment based on entity selection. In one aspect, a method includes the actions of accessing resource data that specifies, for each of a plurality of resources, a resource identifier and one or more referenced entities, and accessing search term data that specifies a plurality of search terms, and for each search term, a selection value for each resource, each selection value being based on user selections of search results that referenced the resource to which the selection value corresponds. From the resource data and search term data, for each search term and each entity, a search term-entity selection value is determined that is based on the selection values of resources that reference the entity and that were referenced by search results in response to a query that included the search term.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: May 28, 2019
    Assignee: Google LLC
    Inventor: Kenichi Kurihara
  • Patent number: 9195462
    Abstract: A technique for tracing processes executing in a multi-threaded processor includes forming a trace message that includes a virtual core identification (VCID) that identifies an associated thread. The trace message, including the VCID, is then transmitted to a debug tool.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: November 24, 2015
    Inventors: Zheng Xu, Suraj Bhaskaran, Jason T. Nearing, Paul B. Rawlins
  • Patent number: 9037796
    Abstract: A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to optimize data remanence over hybrid disk clusters using various storage technologies, determine one or more data storage technologies accessible by a file system, and determine secure delete rules for each of the one or more storage technologies accessible by the file system. The secure delete rules include a number of overwrites required for data to be securely deleted from each of the one or more storage technologies. The programming instructions are further operable to provide the secure delete rules to the file system upon a request for deletion of data for each of the one or more storage technologies a specific amount of times germane to secure delete data from the one or more storage technologies.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Abhinay R. Nagpal, Sandeep R. Patil, Sri Ramanathan, Matthew B. Trevathan
  • Patent number: 8850117
    Abstract: A storage system includes a plurality of storage devices connected together, where the plurality of storage devices include a copy-source storage device having data to be copied and copy-target storage devices capable of receiving the copied data. The copy-source storage device includes a copy-source controller for checking parameters contained in a buffer newly setting command to determine a group of storage devices to be subjected to a newly setting of a buffer and a copy-target storage device in the group and transmitting the parameters to the specified copy-target storage device. The copy-target storage device includes a copy-target controller for performing a buffer newly setting process in the specified copy-target storage device on the basis of the parameters received from the copy-source storage device and notifying the copy-source storage device of a result of the buffer newly setting process.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Limited
    Inventor: Naruhiro Oogai
  • Patent number: 8762642
    Abstract: A multi-cloud data replication method includes providing a data replication cluster comprising at least a first host node and at least a first online storage cloud. The first host node is connected to the first online storage cloud via a network and comprises a server, a cloud array application and a local cache. The local cache comprises a buffer and a first storage volume comprising data cached in one or more buffer blocks of the local cache's buffer. Next, requesting authorization to perform cache flush of the cached first storage volume data to the first online storage cloud. Upon receiving approval of the authorization, encrypting the cached first storage volume data in each of the one or more buffer blocks with a data private key. Next, assigning metadata comprising at lest a unique identifier to each of the one or more buffer blocks and then encrypting the metadata with a metadata private key.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: June 24, 2014
    Assignee: Twinstrata Inc
    Inventors: John W. Bates, Mark Aldred
  • Patent number: 8762620
    Abstract: A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In one embodiment, the storage controller operates with a flash memory module, and includes multiple parallel pipelines that allow plural host commands to be handled simultaneously.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: June 24, 2014
    Assignee: Sandisk Enterprise IP LLC
    Inventors: Douglas A. Prins, Aaron K. Olbrich
  • Patent number: 8688925
    Abstract: For optimized communication between two memory-related processes in a computer system, a synchronization function is coupled with an operating system function such that it withholds an output of an operating system message that signals a data end of a file in a memory region of the computer system. It can thus be avoided that a memory read process interrupts the reading of the file because a memory write process has not yet written all data of the file into the corresponding memory region.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: April 1, 2014
    Assignee: Océ Printing Systems GmbH
    Inventor: Herman Lankreijer
  • Patent number: 8688947
    Abstract: In one or more embodiments, an apparatus comprises an alignment module implemented in hardware to identify requested data that is not aligned on a natural alignment boundary of a memory and load at least two sets of neighboring data such that each said set includes at least a portion of the requested data. The alignment module is further configured to extract the requested data from the at least two sets of neighboring data and output the extracted data to a processor.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: April 1, 2014
    Assignee: Marvell International Ltd.
    Inventors: Anitha Kona, Moinul H. Khan, Bradley C. Aldrich
  • Patent number: 8688903
    Abstract: An associative list processing unit and method comprising employing a plurality of prioritized cell blocks and permitting inserts to occur in a single clock cycle if all of the cell blocks are not full.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: April 1, 2014
    Assignee: Sandia Corporation
    Inventors: Karl Scott Hemmert, Keith D. Underwood
  • Patent number: 8677095
    Abstract: An apparatus and method to allocate memory in a storage system. Firmware running the method uses an iterative approach to find the best optimal memory configuration for a particular storage system given a variety of configuration data parameters stored as persistent data in non-volatile flash memory. The configuration data relates to resources in the environment that the storage system is found in, such as the number of virtual ports, targets and initiators supported by a storage system IOC. The configuration data is alterable, to allow flexibility in updating and changing parameters, and is employed at runtime when the storage system powers on, to enable the most flexible resource allocation.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: March 18, 2014
    Assignee: LSI Corporation
    Inventors: Roger T. J Clegg, Brad D. Besmer, Guy Kendall
  • Patent number: 8677050
    Abstract: According to one aspect of the present disclosure, a method and technique for using processor registers for extending a cache structure is disclosed. The method includes identifying a register of a processor, identifying a cache to extend, allocating the register as an extension of the cache, and setting an address of the register as corresponding to an address space in the cache.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wen-Tzer T. Chen, Diane G. Flemming, William A. Maron, Mysore S. Srinivas, David B. Whitworth
  • Patent number: 8677076
    Abstract: The system described herein may track references to a shared object by concurrently executing threads using a reference tracking data structure that includes an owner field and an array of byte-addressable per-thread entries, each including a per-thread reference counter and a per-thread counter lock. Slotted threads assigned to a given array entry may increment or decrement the per-thread reference counter in that entry in response to referencing or dereferencing the shared object. Unslotted threads may increment or decrement a shared unslotted reference counter. A thread may update the data structure and/or examine it to determine whether the number of references to the shared object is zero or non-zero using a blocking-optimistic or a non-blocking mechanism. A checking thread may acquire ownership of the data structure, obtain an instantaneous snapshot of all counters, and return a value indicating whether the number of references to the shared object is zero or non-zero.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: March 18, 2014
    Assignee: Oracle International Corporation
    Inventors: David Dice, Nir N. Shavit
  • Patent number: 8671264
    Abstract: A storage control device for controlling the storage device including a medium for storing data, logical address information, and address translation information and a memory for storing the address translation information read from the medium includes a first receiver for receiving a write request including logical address information, a first sending module for sending a read request including the logical address information of the write request to the storage device, a second receiver for receiving data and logical address information stored in the medium in accordance with the read request from the storage device, and a second sending module for sending an instruction to cause the storage device to write the address translation information stored in the medium into the memory when the logical address information received by the second receiver is different from logical address information included in the write request.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: March 11, 2014
    Assignee: Fujitsu Limited
    Inventors: Eisaku Takahashi, Teiji Yoshida
  • Patent number: 8661194
    Abstract: A cache control method for a hybrid hard disk drive (HDD) comprising a nonvolatile cache (NVC) and a hard disk. When the hybrid HDD is operating in a non-parallel mode of operation, the control method sequentially searches the NVC and then reads the hard disk for requested data, but when the hybrid HDD is operating in a parallel mode of operation, the control method simultaneously searches the NVC and reads hard disk for the data requested.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: February 25, 2014
    Assignee: Seagate Technology LLC
    Inventor: Hye-jeong Nam
  • Patent number: 8661179
    Abstract: A cache memory architecture, a method of operating a cache memory and a memory controller. In one embodiment, the cache memory architecture includes: (1) a segment memory configured to contain at least one most significant bit (MSB) of a main memory address, the at least one MSB being common to addresses in a particular main memory logical segment that includes the main memory address, (2) a tag memory configured to contain tags that include other bits of the main memory address and (3) combinatorial logic associated with the segment memory and the tag memory and configured to indicate a cache hit only when both the at least one most significant bit and the other bits match a requested main memory address.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: February 25, 2014
    Assignee: Agere Systems LLC
    Inventors: Allen B. Goodrich, Alex Rabinovitch, Assaf Rachlevski, Alex Shinkar
  • Patent number: 8656105
    Abstract: A second level memory controller uses shadow tags 711 to implement snoop read and write coherence. These shadow tags are generally used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. The shadow tags are updated on all level one cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM. These interactions happen on different interfaces, but the traffic on that interface includes level one data cache accesses to both external and level two directly addressable lines. These interactions create extra traffic on these interfaces and creating extra stalls to the CPU. Thus in this invention shadow tags are updated only on a subset of less than all updates of the level one tags.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: February 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Raguram Damodaran, Abhijeet Ashok Chachad, Joseph Raymond Michael Zbiciak, Jonathan (Son) Hung Tran