Patents Examined by Alfredo Bermudez Lozada
  • Patent number: 10037785
    Abstract: Examples include apparatuses and methods related to scan chain operation in sensing circuitry. A number of embodiments include an apparatus comprising an array of memory cells coupled to sensing circuitry having a sense amplifier and a compute component, the sensing circuitry to receive a scan vector and perform a scan chain operation on the scan vector.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: July 31, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Joshua E. Alzheimer, Debra M. Bell
  • Patent number: 10026490
    Abstract: A memory device and a programming method thereof are provided, and the programming method of the memory device includes following steps. A memory cell grouping procedure is performed to divide a plurality of memory cells into a plurality of groups. After the memory cell grouping procedure is performed, a programming procedure is performed, and the programming procedure includes following steps. A first programming pulse, a second programming pulse and a verification pulse are provided to a word line. A first group is programmed by the first programming pulse, and a second group is programmed by the second programming pulse. Whether the first group and the second group respectively pass a verification operation is determined by the verification pulse.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: July 17, 2018
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ya-Jui Lee, Kuan-Fu Chen
  • Patent number: 10026487
    Abstract: A non-volatile memory system includes one or more control circuits configured to program memory cells and verify the programming. The verifying of the programmed memory cells includes applying one or more voltages to perform boosting of a channel region associated with unselected memory cells, allowing the boosting of the channel region for a portion of time while applying the one or more voltages, preventing/interrupting the boosting of the channel region while applying the one or more voltages for a duration of time based on position of a memory cell selected for verification, applying a compare signal to the memory cell selected for verification, and performing a sensing operation for the memory cell selected for verification in response to the compare signal.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: July 17, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hong-Yan Chen, Yingda Dong
  • Patent number: 10020036
    Abstract: One embodiment of the present invention sets forth a method for accessing non-contiguous locations within a DRAM memory page by sending a first column address command to a first DRAM device using a first subset of pins and sending a second column address command to a second DRAM device using a second subset of repurposed pins. The technique requires minimal additional pins, space, and power consumption. Further, sending multiple column address commands allows for increased granularity of DRAM accesses and therefore more efficient use of pins. The technique for accessing non-contiguous locations within a DRAM memory page.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: July 10, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Alok Gupta, Wishwesh Gandhi, Ram Gummadi
  • Patent number: 10020030
    Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a plurality of memory blocks. The semiconductor apparatus may include a peripheral circuit region arranged between the plurality of memory blocks. A plurality of signal input/output (I/O) pads may be arranged in the plurality of memory blocks.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 10, 2018
    Assignee: SK hynix Inc.
    Inventors: Seung Bong Kim, Geun Il Lee
  • Patent number: 10014063
    Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 3, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Huai-Yuan Tseng, Deepanshu Dutta, Tai-Yuan Tseng, Grishma Shah, Muhammad Masuduzzaman
  • Patent number: 10014070
    Abstract: Methods and memories for verifying data path integrity are provided. In one such method, a first set of data are read from a first register of a memory device while a second set of data are written to an array of the memory device. The read first set of data and the data written to the first register are compared to verify data path integrity.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Terry Grunzke
  • Patent number: 10014060
    Abstract: A memory system and method for reducing read disturb errors are disclosed. In one embodiment, a memory system is provided comprising a plurality of blocks of memory and a controller. The controller is configured to detect a read disturb error in a block, identify data that caused the read disturb error, and move the data that caused the read disturb error to a block with a higher read endurance. This can be done by assigning read counters to blocks to determine frequently-read data, and storing that data in a separate block until it is less frequently read and will likely not cause additional read disturb errors.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: July 3, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel E. Tuers, Abhijeet Manohar, Nicholas Thomas, Jonathan Hsu
  • Patent number: 10008265
    Abstract: A memory system is configured to store information using a hybrid volatile and nonvolatile memory device. The memory system, in one aspect, includes memory components, a drain select gate (“DSG”) transistor, and a capacitor component. Each memory component, in one example, includes a source terminal, a gate terminal, a drain terminal, and a nonvolatile cell. The memory components are organized in a string formation and the components are interconnected between source terminals and drain terminals. The drain terminal of DSG transistor is coupled to the source terminal of a memory component and the gate terminal of DSG transistor is coupled to a DSG signal. The drain terminal of the capacitor is coupled to the source terminal of the first DSG transistor. The capacitor component is configured to perform a dynamic random-access memory (“DRAM”) function.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: June 26, 2018
    Assignee: NEO Semiconductor, Inc.
    Inventor: Fu-Chang Hsu
  • Patent number: 10002664
    Abstract: The invention more particularly relates to a resistive memory cell comprising a first and a second metal electrodes and a solid electrolyte positioned between the first and the second metal electrodes, with the solid electrolyte comprising a commutation layer in contact with the first electrode and a dielectric layer, with said resistive memory cell being able to be electrically modified so as to switch from a first resistive state to a second resistive state (state LRS) wherein the resistance (RON) of the memory cell is at least ten times smaller than the resistance (ROFF) of the memory cell in the HRS state, in the LRS state the first electrode being so arranged as to supply metal ions intended to form at least a conductive filament through said commutation layer, with the cell being characterized in that, in the LRS state, the memory cell is conductive for a range of voltages between 0 Volts and VREST 2 .
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: June 19, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Elisa Vianello, Gabriel Molas, Giorgio Palma, Olivier Thomas
  • Patent number: 9990988
    Abstract: A determination can be made as to whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. A signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley can be transmitted.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: June 5, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak, Robert B. Eisenhuth
  • Patent number: 9984742
    Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
  • Patent number: 9978432
    Abstract: Apparatus, systems, and methods for write operations in spin transfer torque (STT) memory are described. In one embodiment, a memory comprises at least one spin-transfer torque (STT) memory device, temperature sensor proximate the STT memory device and a controller comprising logic, at least partially including hardware logic, to monitor an output of the temperature sensor, implement a first write operation protocol when the output of the temperature sensor fails to exceed a threshold temperature, and implement a second write operation protocol when the output of the temperature sensor exceeds the threshold temperature. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventor: Helia Naeimi
  • Patent number: 9978430
    Abstract: A memory system includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Sung Seo, Chul-Woo Park, Hong-Sun Hwang
  • Patent number: 9972379
    Abstract: First and second read requests are received. First data is fetched in response to the first read request. The fetched first data is then stored. The fetched first data corresponds to an address of the first read request. The fetched first data is returned in response to the second read request.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: May 15, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Gregg B. Lesartre
  • Patent number: 9966143
    Abstract: A solid state drive (SSD) with improved power efficiency includes one or more non-volatile memory devices configured to operate according to a programming voltage for a program function or an erase function and to a supply voltage for a read function. The SSD also includes a voltage regulator, external of the one or more non-volatile memory devices, having an output connected to the one or more non-volatile memory devices to supply the programming voltage and an input connected to receive a first voltage, the voltage regulator configured to convert the first voltage to the programming voltage. A discrete capacitor is connected to supply the first voltage to the voltage regulator. The one or more non-volatile memory devices operate according to the programming voltage supplied by the voltage regulator during both the normal operation of the SSD and in the event of a power loss or failure of the SSD.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: May 8, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Stephen K. Pardoe
  • Patent number: 9953700
    Abstract: A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 24, 2018
    Assignee: SK Hynix Inc.
    Inventor: Bo-Kyeom Kim
  • Patent number: 9905307
    Abstract: Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. One example of the conductive region is a common source line that includes one or more local source lines and one or more global source lines. If the leakage current were to become high enough, the electrical short between the conductive region and the block select line could cause a plane level failure. If the leakage current is less than an amount that would cause a plane failure, but that indicates that the non-volatile memory device is susceptible to a plane failure, data may be moved out of the plane before the plane failure occurs. Thus, data loss may be prevented.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: February 27, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Ashish Ghai, Lakshmi Kalpana Vakati, Ekamdeep Singh, Chang Siau, Gopinath Balakrishnan, Kapil Verma
  • Patent number: 9875807
    Abstract: A semiconductor memory apparatus may include a data conversion control block configured to control the number of pipe input control signals and the number of pipe output control signals which are enabled, in response to a training control signal. The semiconductor memory apparatus may also include a data conversion block configured to receive parallel data and output serial data, in response to the pipe input control signals and the pipe output control signals.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: January 23, 2018
    Assignee: SK hynix Inc.
    Inventor: Jae Il Kim
  • Patent number: 9870826
    Abstract: A memory apparatus and a data access method thereof are provided. The memory apparatus includes a first memory unit and a second memory unit, wherein an access speed of the second memory unit is higher than an access speed of the first memory unit. The method includes: receiving write data and a corresponding write address; comparing the write data with data corresponding to the write address in the second memory unit, so as to determine whether to write the write data into a current physical memory page of the first memory unit and into the second memory unit; after a data writing operation is executed, executing a data arranging operation on the current physical memory page according to the data in the second memory unit when the current physical memory page is full; and when a read command is received, reading the corresponding data in the second memory unit.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: January 16, 2018
    Assignee: Nuvoton Technology Corporation
    Inventors: Chang-Hong Lin, Chun-Hao Huang, Chieh-Sheng Tu