Patents Examined by Alice W. Tang
  • Patent number: 5760417
    Abstract: In a semiconductor electron emission device for causing an avalanche breakdown by applying a reverse bias voltage to a Schottky barrier junction between a metallic material or metallic compound material and a p-type semiconductor, and externally emitting electrons from a solid-state surface, a p-type semiconductor region (first region) for causing the avalanche breakdown contacts a p-type semiconductor region (second region) for supplying carriers to the first region, and a semi-insulating region is formed around the first region.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: June 2, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuo Watanabe, Norio Kaneko, Masahiko Okunuki, Takeo Tsukamoto
  • Patent number: 5760463
    Abstract: A superconductor device which includes a first wiring part and a second wiring part which together form a superconductive wiring. The first wiring part is arranged onto a substrate and is made of a superconductor material. The second wiring part is made of a non-oxide semiconductor material. The second wiring part is adjacent to the first wiring part and jointly forms a superconductive wiring with the first wiring part by becoming at least partly superconductive due to proximity effect with the first wiring part. The second wiring part has a smaller penetration length of magnetic field than that for the first wiring part. This structure enhances the propagation velocity of a signal within the superconductive wiring.
    Type: Grant
    Filed: February 14, 1996
    Date of Patent: June 2, 1998
    Assignee: Fujitsu Limited
    Inventor: Tsunehiro Hato
  • Patent number: 5760452
    Abstract: Disclosed are an improved semiconductor memory cell suitable for high integration and a novel method of fabricating the same. The memory cell has a large capacitance and a small area. The memory cell also has a plurality of bit-lines buried in an isolation region in a semiconductor substrate. The bit-line has a very small width and thickness thereby reducing a parasitic capacity between the bit-line and the semiconductor substrate. The memory cell may further be provided with a noise shielding line. Further, disclosed is a novel memory cell array of a semiconductor memory. The buried bit-line is coupled with a bit-line connecting sub-arrays and both are separated by a insulation film. A plurality of pairs of the bit-lines are arranged in rows. A word-line is coupled with a sub-word line and both are separated by a insulation film. A plurality of pairs of the word-lines are arranged in columns. The memory cells are arranged at the intersections of the buried bit-lines and the word-lines.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: June 2, 1998
    Assignee: NEC Corporation
    Inventor: Kazuo Terada
  • Patent number: 5753935
    Abstract: In a radiation detection device using superconducting tunnel junctions, the increase in electric capacitance and the decrease in electric resistance due to the increase in junction area for improvement of the detection efficiency are largely repressed by the invention. The junctions are connected in series. The number of the series-connected junctions is settled in the range of larger than 0.05 (SC.sub.o /C')0.5 and smaller than 20 (SC.sub.o /C')0.5 or 10SCo/C', whichever is larger, where S is the total area of the junctions, cm.sup.2, C.sub.o is the electric capacitance per unit area of the junctions, F/cm.sup.2, and C' is the electric capacitance connected to the device in parallel so as to transfer and amplify the signals from the device, F.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: May 19, 1998
    Assignee: Nippon Steel Corporation
    Inventors: Masahiko Kurakado, Atsuki Matsumura, Tooru Takahashi
  • Patent number: 5739580
    Abstract: A process and resulting product is described for forming an oxide in a semiconductor substrate which comprises initially implanting the substrate with atoms of a noble gas, then oxidizing the implanted substrate at a reduced temperature, e.g., less than C., to form oxide in the implanted region of the substrate, and then etching the oxidized substrate to remove a portion of the oxide. The resulting oxidation produces a dual layer of oxide in the substrate. The upper layer is an extremely porous and frothy layer of oxide, while the lower layer is a more dense oxide. The upper porous layer of oxide can be selectively removed from the substrate by a mild etch, leaving the more dense oxide layer in the substrate. Further oxide can then be formed adjacent the dense layer of oxide in the substrate, either by oxide deposition over the dense oxide or by growing further oxide beneath the dense oxide layer.
    Type: Grant
    Filed: January 27, 1997
    Date of Patent: April 14, 1998
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, James Kimball
  • Patent number: 5736755
    Abstract: Disclosed are devices having emitters having resistive emitter diffusion sections are in a radial pattern. Such devices include vertical PNP power devices. The radial pattern of holes defines resistive emitter diffusion sections between adjacent holes. The resistive emitter diffusion sections result in a lower emitter ballast resistance due to the higher emitter sheet resistance of PNP devices. This allows all the periphery of the emitter to be active, not just two sides. The device has improved emitter ballast resistance while at the same time remaining efficient with low saturation resistance.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: April 7, 1998
    Assignee: Delco Electronics Corporation
    Inventors: John Rothgeb Fruth, John Kevin Kaszyca, Mark Wendell Gose
  • Patent number: 5721196
    Abstract: A Josephson junction device comprises a single crystalline substrate including a principal surface, an oxide layer formed on the principal surface of the substrate having a step on its surface and an oxide superconductor thin film formed on the surface of the oxide layer. The oxide superconductor thin film includes a first and a second portions respectively positioned above and below the step of the oxide layer, which are constituted of single crystals of the oxide superconductor, and a step-edge junction made up of a grain boundary on the step of the oxide layer, which constitutes a weak link of the Josephson junction.
    Type: Grant
    Filed: August 16, 1996
    Date of Patent: February 24, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5719105
    Abstract: A superconducting element is disclosed which includes a substrate and a superconducting layer provided on the substrate and formed of an oxide having the following chemical formula:RBa.sub.2 (Cu.sub.1-x M.sub.x).sub.3 O.sub.7wherein R represents at least one element selected from the group consisting of Y, La, Nd, Pm, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, M represents at least one element selected from the group consisting of Al, Ti, V, Cr, Mn, Fe, Co, Ni, Zn and Ga, and x represents a number of less than 1 but greater than 0.
    Type: Grant
    Filed: October 24, 1994
    Date of Patent: February 17, 1998
    Assignees: International Superconductivity Technology Center, Matsushita Electric Industrial Co., Ltd., Sanyo Electric Co., Ltd.
    Inventors: Akihiro Odagawa, Youichi Enomoto, Shuuichi Yoshikawa
  • Patent number: 5710441
    Abstract: A microcavity LED with photon recycling including a substrate having at least one layer of material positioned thereon, and a first cladding layer, a second cladding layer and an active region sandwiched therebetween forming a mesa on the layer of material. The mesa has generally vertical sides and an upper surface with an electrically conductive and light reflective system positioned on the vertical sides of the mesa and partially covering the upper surface to form a first electrical contact for the LED, the electrically conductive and light reflective system defining a centrally located light emitting opening on the surface of the mesa, the mesa having a diametric dimension of the surface greater than one time larger than a diametric dimension of the opening.
    Type: Grant
    Filed: October 30, 1995
    Date of Patent: January 20, 1998
    Assignee: Motorola, Inc.
    Inventors: Donald E. Ackley, Chan-Long Shieh, Michael S. Lebby
  • Patent number: 5708281
    Abstract: A semiconductor device comprises an emitter of first conductivity type, a base of second conductivity type, and a collector of first conductivity type. At least a vicinity of an interface of the emitter to base junction is formed by Si. Polycrystalline or single crystalline Si.sub.1-x C.sub.x (x.ltoreq.0.5) is formed on a region formed by the Si of said emitter. A junction between a region of the Si and a region of the polycrystalline and the single crystalline Si.sub.1-x C.sub.x is a graded hetero junction.
    Type: Grant
    Filed: March 14, 1994
    Date of Patent: January 13, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masakazu Morishita
  • Patent number: 5696392
    Abstract: A conductor suitable for use in oxide-based electronic devices and circuits is disclosed. Metallic oxides having the general composition AMO.sub.3, where A is a rare or alkaline earth or an alloy of rare or alkaline earth elements, and M is a transition metal, exhibit metallic behavior and are compatible with high temperature ceramic processing. Other useful metallic oxides have compositions (A.sub.1-x A'.sub.x)A".sub.2 (M.sub.1-y M'.sub.y).sub.3 or (A.sub.1-x A'.sub.x).sub.m (M.sub.1-y M'.sub.y).sub.n O.sub.2m+n, where 0.ltoreq.x, y.ltoreq.1 and 0.5.ltoreq.m, n.ltoreq.3, A and A' are rare or alkaline earths, or alloys of rare or alkaline earths, A' and A" are alkaline earth elements, alloys of alkaline earth elements, rare earth elements, alloys of rare earth elements, or alloys of alkaline earth and rare earth elements, and M and M' are transition metal elements or alloys of transition metal elements.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: December 9, 1997
    Assignee: Conductus, Inc.
    Inventors: Kookrin Char, Theodore H. Geballe, Brian H. Moeckly
  • Patent number: 5693595
    Abstract: A termination for a high-temperature superconductive thin-film microwave device formed on the obverse side of a substrate with the reverse side of the substrate having a ground plane. The termination can include a thin-film resistor being integral with an operative component, with the substrate being a preselected dielectric substrate. The resistor can have an epitaxially-formed layer of molybdenum metal of a first preselected thickness on the obverse side, and an epitaxially-formed layer of titanium metal of a second preselected thickness thereon. The termination includes a epitaxially-formed thin-film capacitor integral with the resistor. The capacitor can have a layer of titanium metal formed on a portion of the obverse side with a layer of gold metal formed thereon. The substrate can be lanthanum aluminate, and the high-temperature superconductive film can be a yttrium-barium-copper-oxide film. The ground plane can be made of a high-temperature superconductive film and annealed gold.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: December 2, 1997
    Assignee: Northrop Grumman Corporation
    Inventors: Salvador H. Talisa, Daniel L. Meier
  • Patent number: 5684315
    Abstract: A semiconductor memory device has memory cells provided at intersections between word line conductors and data line conductors. Each of the memory cells includes a cell selecting transistor and an information storage capacitor. The capacitor in each of the memory cells includes a first capacitor component formed over the control electrode of the transistor and a second capacitor component formed over a word line conductor which is adjacent to a word line conductor integral with the control electrode of the transistor. Each of the first and second capacitor components has a common electrode, a storage electrode and a dielectric film sandwiched therebetween, and the storage electrode is at a level higher than the common electrode in each of said first and second capacitor components. The storage electrodes of the first and second capacitor components are electrically connected with each other and with one of the semiconductor regions of the transistor.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: November 4, 1997
    Assignees: Hitachi, Ltd., Hitachi Instruments Engineering Co., Ltd., Hitachi ULSI Engineering Corporation, Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Hiroyuki Uchiyama, Yoshiyuki Kaneko, Hiroki Soeda, Yasuhide Fujioka, Nozomu Matsuda, Motoko Sawamura
  • Patent number: 5675161
    Abstract: Improved non-volatile memory cells capable of being written and erased electrically, suitable for high density low voltage applications are disclosed. Writing the cells is by using the Channel Accelerated Carrier Tunneling (CACT) method for programming memories, (patent application Ser. No. 08/209,787 filed on Mar. 11, 1994) and the erase is by tunneling through a thin oxide region. Two structural embodiments are disclosed. First embodiment, Trenched-Channel Accelerated Tunneling Electron cell (Tr.sub.-- CATE), and a second embodiment Trench Wall-Channel Accelerated Tunneling Electron cell (Tw-CATE), both make use of separate regions of the channel for write and erase and hence provide high reliability of operation. The cells disclosed use a vertical step etch to form part of the channel to accelerate the carriers and also to act as a select gate without increasing the cell area.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: October 7, 1997
    Inventor: Mammen Thomas
  • Patent number: 5670803
    Abstract: A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors ("FETs") buried within a single trench. Specifically, two FETs are located at each of two sidewalls of the trench with one FET being disposed above the other FET at each sidewall. Coaxial wiring electrically cross-couples the FETs within the trench such that a pair of cross-coupled inverters comprising the storage flip-flop for the SRAM cell is formed. A fifth, I/O transistor is disposed at the top of the trench structure, and facilitates access to the flip-flop. Specific details of the SRAM trench structure, and fabrication methods therefor are also set forth.
    Type: Grant
    Filed: February 8, 1995
    Date of Patent: September 23, 1997
    Assignee: International Business Machines Corporation
    Inventors: Kenneth Edward Beilstein, Jr., Claude Louis Bertin, John Edward Cronin, Francis Roger White
  • Patent number: 5654259
    Abstract: The substance has a composition of a general chemical formula ofBi.sub.2 -(Sr.sub.2 Ca.sub.1).sub.1-x (La.sub.2 Y.sub.1).sub.x -Cu.sub.y -O.sub.z,where 0.4.ltoreq.x.ltoreq.1, y=2 and z=9-10.5, wherein the substance is an insulator or a semiconductor in the dark, and has a photoconductivity Q(.lambda.,T) in conjugate with superconductivity of a superconductor of an adjacent component of the Bi-SrCa-LaY-Cu-O system at and below a critical temperature (T) of less than K. and below K. at photoexcitation in an optical wavelength range (.lambda.) of 420-670 nm. The present invention relates to a method for producing the same and a superconductive optoelectronic device by using the same. The present invention also relates to an organized integration of the element or device into an apparatus to further develop a new field of "Superconductive Optoelectronics.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 5, 1997
    Assignee: The University of Tokyo
    Inventor: Taizo Masumi
  • Patent number: 5648662
    Abstract: A method of fabricating silicon TFTs (thin-film transistors) is disclosed. The method comprises a crystallization step by laser irradiation effected after the completion of the device structure. First, amorphous silicon TFTs are fabricated. In each of the TFTs, the channel formation region, the source and drain regions are exposed to laser radiation illuminated from above or below the substrate. Then, the laser radiation is illuminated to crystallize and activate the channel formation region, and source and drain regions. After the completion of the device structure, various electrical characteristics of the TFTs are controlled. Also, the amorphous TFTs can be changed into polysilicon TFTs.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: July 15, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Naoto Kusumoto
  • Patent number: 5627139
    Abstract: A HTSC Josephson device wherein the barrier layer is a cubic, conductive material.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: May 6, 1997
    Assignee: The Regents of the University of California
    Inventors: David K. Chin, Theodore Van Duzer
  • Patent number: 5625233
    Abstract: The use of a bi-layer thin film structure consisting of aluminum or aluminide on a refractory metal layer as a diffusion barrier to oxygen penetration at high temperatures for preventing the electrical and mechanical degradation of the refractory metal for use in applications such as a capacitor electrode for high dielectric constant materials.
    Type: Grant
    Filed: January 13, 1995
    Date of Patent: April 29, 1997
    Assignee: IBM Corporation
    Inventors: Cyril Cabral, Jr., Evan G. Colgan, Alfred Grill
  • Patent number: 5612290
    Abstract: A Josephson junction device is disclosed that includes a single crystalline substrate having a NaCl type crystal structure. The device includes a principal surface having two horizontal planes and a slope inclined at an angle of to between the two horizontal planes. An oxide superconductor thin film is formed on the principal surface of the substrate, which includes first and a second superconducting portions of a first single crystalline oxide superconductor and a second single crystalline oxide superconductor respectively positioned on the two horizontal planes of the substrate. A junction portion of a single crystalline oxide superconductor has a different crystal orientation from the first and the second superconducting portions, and is positioned on the slope of the substrate. Two grain boundaries between each of the first and the second superconducting portions and the junction portion constitute one weak link of the Josephson junction.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: March 18, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Saburo Tanaka, Takashi Matsuura, Hideo Itozaki