Abstract: A ferroelectric memory cell has an FET covered by an insulation layer and a ferroelectric capacitor located thereover. An interconnect couples an upper plate of the ferroelectric capacitor to a source/drain of the transistor. In a method of forming the cells, after the transistor is fabricated, the bottom electrode and ferroelectric dielectric are established, but the top capacitor electrode is not added until a further layer of insulation is added over the ferroelectric and windows are opened in it. One window is for the top electrode and another window is to one source/drain region of the FET.
Abstract: A collector-up bipolar transistor having an undercut region (522) beneath extrinsic regions of a base layer (510) and an emitter layer (508). The extrinsic emitter region is depleted of charge carriers and provides passivation for the extrinsic portion of the base layer (508). Contact to the emitter layer may be made by forming contacts on the top surface of the substrate (500) or in a recess in the backside of the substrate.
Abstract: A photo sensor comprises a semiconductor substrate, a bipolar photo transistor having an emitter region, a base region and a collector region which is formed in the surface region of the semiconductor substrate, a silicon dioxide formed on the bipolar phototransistor, and a film having a smaller diffusion coefficient of hydrogen than the silicon dioxide formed all over the silicon dioxide.
Abstract: A flash memory cell includes the usual thermal oxide layer deposited above the substrate including the source and the drain. On the thermal oxide layer, a silicon rich oxide layer is formed. Above the silicon rich oxide layer a gate structure is formed of layer of polysilicon separated by an intermediate dielectric layer. The lower polysilicon layer commences as an initial portion of the layer of small grain size followed by either amorphous or large grain size material.
Abstract: A superconductor device is provided including a base, a base electrode formed on the base which is made of a Bi-system oxide superconductive material containing an alkaline earth metal, a barrier layer formed on the base electrode which is made of Bi--Sr--Cu--O, a counter electrode formed on the barrier layer which is made of a Bi-system oxide superconductive material containing an alkaline earth metal, a contact electrode formed so as contact with the counter electrode, and a separation layer for separating said contact electrode from said base electrode.
January 21, 1994
Date of Patent:
January 2, 1996
Matsushita Electric Industrial Co., Ltd.
Abstract: An object of the present invention is to provide a semiconductor device which is designed so as to increase a maximum controllable current and decrease hold current without degrading its characteristic and to provide a method of manufacturing such a semiconductor device. A transistor formation region 3 and a P diffusion region 15 are selectively formed through an insulating film 4 between gate electrodes 5 on an N.sup.- epitaxial layer 2. In a transistor formation region 3, an N.sup.+ diffusion region 12 is formed on a P diffusion region 11, a P diffusion region 13 is formed on the N.sup.+ diffusion region 12, and an N.sup.+ diffusion region 14 is selectively formed on a surface of the P diffusion region 13. Then, a cathode electrode 7 is formed on the P diffusion region 13, N.sup.+ diffusion region 14 and P diffusion region 15, and an anode electrode 8 is formed on a second major surface of the P.sup.+ substrate 1.
Abstract: A Josephson device comprises a first electrode layer of a superconducting material and containing Nb therein as a constituent element, an overlayer of a nitride of a refractory metal element provided on the first electrode layer, a barrier layer of an insulating compound that contains the metal element as a constituent element and acting as a barrier of a Josephson junction, the barrier layer being provided on the overlayer, and a second electrode layer of a superconducting material and containing Nb therein as a constituent element, the second electrode layer being provided on the barrier layer.
Abstract: An insulated-gate bipolar transistor (IGBT) is connected in reverse-parallel with a current-regenerative diode which, for economy of manufacture, is integrated with the IGBT. Such a diode may extend laterally on an IGBT chip, with two conductivity regions forming the diode respectively connected to emitter and collector electrodes of the IGBT. Alternatively, the diode may be formed by short-circuiting a buffer layer and a collector layer. By such integration, greater device packing density can be realized.
Abstract: An anisotropic superconductor junction device consisting of a lower superconducting layer and an upper superconducting layer separated by a barrier layer, in which the upper and lower superconducting layers and the barrier layer each have a (103) crystal orientation in which the c axis is arranged in the same direction at an angle of 45 degrees relative to the plane of the junction.
March 18, 1994
Date of Patent:
December 5, 1995
Agency of Industrial Science & Technology, Ministry of International Trade & Industry
Abstract: The invention relates to a gas sensor comprises a precious metal electrode, a semiconductor layer entirely or partly covering the precious metal electrode, a barrier layer having a high potential formed at an interface between the precious metal electrode and the semiconductor layer.
Abstract: A power semiconductor component having integrated protection against electrostatic destruction is published. Such a semiconductor component (1) comprises a semiconductor substrate (10) having at least one MOS structure whose gate (7) is arranged insulated from the semiconductor substrate (10). Such structures are susceptible to destruction by a dielectric breakdown of the insulation layer, caused by electrostatic charging. According to the invention, this insulating layer between-the gate electrode (3) and the main electrode (2) is now replaced by a semi-insulating layer (9) so that a limited current flow becomes possible between the gate (7) and the main electrode (2) and it is no longer possible for any potential difference to build up.
Abstract: Voltage breakdown resistant monocrystalline silicon carbide semiconductor devices are obtained by forming an amorphous silicon carbide termination region in a monocrystalline silicon carbide substrate, at a face thereof, adjacent and surrounding a silicon carbide device. The amorphous termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize the substrate face. The device contact or contacts act as an implantation mask to provide a self-aligned termination region for the device. The terminated devices may exhibit voltage breakdown resistance which approaches the ideal value for silicon carbide.
Abstract: For manufacturing a superconducting device, a first oxide superconductor thin film having a very thin thickness is formed on a principal surface of a substrate, and a stacked structure of a gate insulator and a gate electrode is formed on a portion of the first oxide superconductor thin film. A second oxide superconductor thin film is grown on an exposed surface of the first oxide superconductor thin film, using the gate electrode as a mask, so that first and second superconducting regions having a relatively thick thickness are formed at opposite sides of the gate electrode, electrically isolated from the gate electrode. A source electrode and a drain electrode are formed on the first and second oxide superconducting regions. The superconducting device thus formed can function as a super-FET.
Abstract: A super-capacitor comprising a positive electrode, a negative electrode, both made of a p-doped electron conductive polymer, and an electrolyte. The electrolyte comprises an organic redox compound soluble in the electrolyte in an amount of at least 10.sup.-3 mole per liter. The redox potential of the redox compound lies in a non-capacitive region of the electron conductive polymer. The redox compound is reduced in a reversible manner at the negative electrode when the potential of the negative electrode is equal to or less than the redox potential of the redox compound, and the redox compound is oxidized in a reversible manner at the positive electrode when the potential of the positive electrode is equal to or more than the redox potential of the redox compound.
December 10, 1992
Date of Patent:
August 15, 1995
Alcatel Alsthom Compagnie Generale D'Electricite
Abstract: A heterostructure includes a stained epitaxial layer of either silicon or germanium that is located overlying a silicon substrate, with a spatially graded Ge.sub.x Si.sub.1-x epitaxial layer overlain by a ungraded Ge.sub.x.sbsb.0 Si.sub.1-x.sbsb.0 intervening between the silicon substrate and the strained layer. Such a heterostructure can serve as a foundation for such devices as surface emitting LEDs, either n-channel or p-channel silicon-based MODFETs, and either n-channel or p-channel silicon-based MOSFETs.
August 9, 1993
Date of Patent:
August 15, 1995
Daniel Brasen, Eugene A. Fitzgerald, Jr., Martin L. Green, Donald P. Monroe, Paul J. Silverman, Ya-Hong Xie
Abstract: A SQUID comprises a substrate, a washer of an oxide superconductor thin film formed on a principal surface of the substrate, a hole shaped a similar figure to the washer at the center of the washer, a slit formed between one side of the washer and the hole, and a Josephson junction which connects portions of the washer at the both sides of the slit across the slit. In the SQUID, the ratio of similarity of the washer to the hole ranges 100 to 2500.
Abstract: The invention is a resonant tunnel effect quantum well transistor. To improve the gain by avoiding the storage of charges in the well, which consists of layer (14) with a narrow forbidden band and two barriers (13, 15) with a wide forbidden band, the quantum well is laterally bounded--in the plane of the layers--by a depleted region (22) which forms a quantum box whose dimensions are smaller than the De Broglie wavelength. Application to fast electronics (200 GHz).
Abstract: A superconducting multilayer interconnection comprises a substrate having a principal surface, a first superconducting current path of a c-axis orientated oxide superconductor thin film formed on the principal surface of the substrate, an insulating layer on the first superconducting current path, and a second superconducting current path of a c-axis orientated oxide superconductor thin film formed on the insulating layer so that the first and second superconducting current paths are insulated by the insulating layer. The superconducting multilayer interconnection further comprises a superconducting interconnect current path of an a-axis orientated oxide superconductor thin film, through which the first and second superconducting current paths are electrically connected each other.
Abstract: A superconducting thin film formed on a substrate, comprising an a-axis orientated oxide superconductor layer, a c-axis orientated oxide superconductor layer and an oxide semiconductor layer inserted between the a-axis orientated oxide superconductor layer and the c-axis orientated oxide superconductor layer, in contact with them in which superconducting current can flow between the a-axis orientated oxide superconductor layer and the c-axis orientated oxide superconductor layer through the oxide semiconductor layer by a long-range proximity effect.
Abstract: A static induction thyristor has a first semiconductor area having a high impurity concentration of a first conductivity type. A second semiconductor area having low impurity concentration is formed adjacent to the first semiconductor area. A third semiconductor area having a high impurity concentration of a second conductivity type which is the conductivity type opposite to the first conductivity type is formed on a part of a surface of the second semiconductor area so located as to form a fourth semiconductor area located within the third semiconductor area. A fifth semiconductor area having a high impurity concentration of the first conductivity type is formed on the part of the surface of the second semiconductor area in spaced relation to the forth semiconductor area.