Abstract: In one embodiment, there is provided a non-volatile magnetic memory cell. The non-volatile magnetic memory cell comprises a switchable magnetic element; and a word line and a bit line to energize the switchable magnetic element; wherein at least one of the word line and the bit line comprises a magnetic sidewall that is discontinuous.

Abstract: A spin electronic memory of the present invention includes: a pair of electrodes 1, 2, recording layers 6a, 6b, and 6c between the electrodes 1 and 2, the recording layer being formed by laminating first alloy layer 5 and second alloy layer 4, the first alloy layer 5 being formed to contain any one of SbTe, Sb2Te3, BiTe, Bi2Te3, BiSe, and Bi2Se3 as a principal component and to have a thickness of 2 nm to 10 nm, the second alloy layer 4 being formed to contain an alloy expressed by general formula (1) as a principal component; and spin injection layer 7 formed with a magnetic material to inject a spin into the recording layer with the magnetic material being magnetized, M1-xTex??(1) where M represents an atom selected from atoms of Ge, Al, and Si, and x represents a value of 0.5 or more and less than 1.

Abstract: A resistive switching memory stack is provided. The resistive switching memory stack includes a bottom electrode, formed from one or more metals. The resistive switching memory stack further includes a metal oxide layer, disposed over the bottom electrode, formed from an Atomic Layer Deposition (ALD) of one or more metal oxides. The resistive switching memory stack also includes a top electrode, disposed over the metal oxide layer, formed from the ALD of a plurality of metals into a metal layer stack. An oxygen vacancy concentration of the resistive switching memory stack is controlled by (i) a thickness of the plurality of metals forming the top electrode and (ii) a percentage of a particular one of the plurality of metals in the metal layer stack of the top electrode.

Abstract: A semiconductor memory device including first lines and second lines overlapping and intersecting each other, variable resistance memory elements disposed at intersections between the first lines and the second lines, and switching elements disposed between the variable resistance memory elements and the first lines. At least one of the switching elements includes first and second chalcogenide compound layers, and conductive nano-dots disposed between the first and second chalcogenide compound layers.

Abstract: A three dimensional (3D) memory array may include a plurality of memory cells. An example 3D memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. A memory cell included in the memory material is aligned in a same plane as the electrode plane, and the memory cell is configured to exhibit a first threshold voltage representative of a first logic state and a second threshold voltage representative of a second logic state. A conductive pillar is disposed through and coupled to the memory cell, wherein the conductive pillar and electrode plane are configured to provide a voltage across the memory cell to write a logic state to the memory cell.

Abstract: Resistive RAM (RRAM) devices having increased uniformity and related manufacturing methods are described. Greater uniformity of performance across an entire chip that includes larger numbers of RRAM cells can be achieved by uniformly creating enhanced channels in the switching layers through the use of radiation damage. The radiation, according to various described embodiments, can be in the form of ions, electromagnetic photons, neutral particles, electrons, and ultrasound.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a trench formed in a substrate; a gate dielectric layer formed on a surface of the trench; a gate electrode which is formed on the gate dielectric layer, gap-fills a part of the trench, and contains dopants; a diffusion region which is formed to be in contact with the surface of the trench and to correspond to the gate electrode in the substrate; junction regions formed in the substrate at both sides of the trench; and a memory element coupled to a junction region in a side of the trench.

Abstract: The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat. A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.

Abstract: A resistive random-access memory structure and a method for fabricating a resistive random-access memory structure are described. A first dielectric layer is formed on a substrate. A plurality of bottom electrodes are independently embedded in the first dielectric layer. A transition metal oxide layer covers the plurality of bottom electrodes and extends onto a portion of the first dielectric layer. The minimum distance between the bottom electrode and a sidewall of the transition metal oxide layer is a first distance. The first distance is in a range of 10 nm to 200 ?m. A top electrode is formed on the transition metal oxide layer.

Abstract: An electronically programmable read-only memory (EPROM) cell includes a semiconductor substrate having source and drain regions; a floating gate, adjacent to the source and drain regions and separated from the semiconductor substrate by a first dielectric layer, the floating gate including: a polysilicon layer formed over the first dielectric layer; a first metal layer electrically connected to the polysilicon layer, where the surface area of the first metal layer is less than 1000 ?m2; and a control gate comprising a second metal layer, capacitively coupled to the first metal layer through a second dielectric material disposed therebetween.

Abstract: A three dimensional (3D) memory array may include a plurality of memory cells. An example 3D memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. A memory cell included in the memory material is aligned in a same plane as the electrode plane, and the memory cell is configured to exhibit a first threshold voltage representative of a first logic state and a second threshold voltage representative of a second logic state. A conductive pillar is disposed through and coupled to the memory cell, wherein the conductive pillar and electrode plane are configured to provide a voltage across the memory cell to write a logic state to the memory cell.

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

Abstract: A single poly NVM cell includes a first N-type well region and a second N-type well region spaced apart from each other by a P-type semiconductor layer, a first active region and a second active region disposed in the first N-type well region and the second N-type well region, respectively, a P-channel floating gate transistor including a floating gate disposed in the first active region, a P-type drain region disposed in the first active region, and a P-type junction region disposed in the first active region, wherein the floating gate extends to over the second active region, a P-channel read selection transistor including a read selection gate electrode disposed in the first active region, the P-type junction region disposed in the first active region, and a P-type source region disposed in the first active region, and an interconnection line connecting the first N-type well region to the P-type source region of the P-channel read selection transistor.

Abstract: Perpendicular magnetic anisotropy (PMA) type magnetic random access memory cells are constructed with a composite PMA layer to provide a magnetic tunnel junction (MTJ) with an acceptable thermal barrier. A PMA coupling layer is deposited between a first PMA layer and a second PMA layer to form the composite PMA layer. The composite PMA layer may be incorporated in PMA type MRAM cells or in-plane type MRAM cells.

Abstract: Some embodiments include selectively conducting devices having a first electrode, a second electrode, and dielectric material between the first and second electrodes. The dielectric material may be configured to conduct current from the first electrode to the second electrode when a first voltage is applied across the first electrode and the second electrode. Furthermore, the dielectric material may be configured to inhibit current from flowing from the second electrode to the first electrode when a second voltage having a polarity opposite that of a polarity of the first voltage is applied across the first electrode and the second electrode. The diode material may comprise a plurality of layers of different dielectric materials arranged in order of increasing barrier height. Quantum wells may form at junctions of layers of the plurality responsive to the first voltage. Some embodiments include diode forming methods.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an interlayer dielectric layer formed over a substrate and having a contact hole; a contact plug formed in a lower part of the contact hole; a contact pad formed in an upper part of the contact hole; an amorphous buffer layer interposed between the contact plug and the contact pad; and a variable resistance element formed over the contact pad.

Abstract: A plurality of alternating stacks laterally spaced apart by line trenches is provided over a substrate. Each alternating stack includes respective word lines and respective dielectric material layers. An alternating sequence of vertical bit lines and inter-bit-line cavities is formed within each of the line trenches. Resistive memory material layers including resistive memory elements are provided at intersection regions between the word lines and the vertical bit lines. Air gaps are formed by removing at least a predominant portion of each of the dielectric material layers selective to the word lines, the vertical bit lines, and the resistive memory material layers, thereby forming a plurality of alternating stacks of the word lines and air gaps. A dielectric isolation layer including vertically-extending voids can be formed over the plurality of alternating stacks in the inter-bit-line cavities.

Abstract: A mesa structure is formed over peripheral devices on a substrate. An alternating stack of insulating layers and spacer material layers is formed over the substrate and the mesa structure. A region of the alternating stack overlying the mesa structure is removed to provide a region in which the layers in the alternating stack extend along a non-horizontal direction that is parallel to the dielectric sidewall of the mesa structure. Memory stack structures and backside contact via structures are formed through another region of the alternating stack that includes horizontally-extending portions of the layers within the alternating stack. The spacer material layers are provided as, or are replaced with, electrically conductive layers. Top surfaces of portions of the electrically conductive layers that extend parallel to the dielectric sidewall of the mesa structure can be contacted by word line contact via structures.

Abstract: A memory cell includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.