Abstract: The present disclosure provides a static random access memory (SRAM) cell comprising first, second, and third fins defined in various well regions. The fins are spaced from each other along a first direction and extend lengthwise generally along a second direction perpendicular to the first direction. The fins include source, drain, and channel regions for various pull-up, pull-down, and pass-gate fin field-effect transistors (FinFETs). The SRAM cell further includes various gate features over the fins and extending lengthwise generally along the first direction. The gate features include gate regions for the various FinFETs.

Abstract: Embodiments of the inventive concepts provide magnetic memory devices. The magnetic memory device includes a magnetic tunnel junction including a free layer, a pinned layer, and a tunnel barrier layer between the free layer and the pinned layer. The free layer includes a perpendicular magnetic material doped with non-magnetic impurities.

Abstract: A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

Abstract: A storage element and storage devices containing the same, having a layered structure and being configured for storing information are disclosed. In one example, the storage element comprises a storage portion with a storage magnetization that is perpendicular to a film surface of the layered structure, wherein a direction of the storage magnetization is configured to change according to the information. The storage element also includes a fixed magnetization portion with reference magnetization serving as a reference to the storage magnetization, and an intermediate portion between the storage portion and the fixed magnetization portion that is made of a non-magnetic material. The fixed magnetization portion includes a laminated ferrimagnetic structure that comprises a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer. The fixed magnetization portion includes a first magnetic material that is an alloy or a laminated structure including Pt, Co, and Y.

Abstract: A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer?2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=? to ½. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines. M array regions of the N array regions are configured to operate simultaneously. M is an integer. M/N=½ or 1.

Abstract: A device has a M8XY6 layer in between a first conductive layer on the top and a second conductive layer on the bottom, wherein (i) M includes at least one element selected from the following: Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element. Another device has MaXbYc material contacted on opposite sides by respective layers of conductive material, wherein: (i) M includes at least one element selected from the following: Cu, Ag, Li, and Zn, (ii) X includes at least one Group XIV element, and (iii) Y includes at least one Group XVI element, and a is in the range of 48-60 atomic percent, b is in the range of 4-10 atomic percent, c is in the range of 30-45 atomic percent, and a+b+c is at least 90 atomic percent.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first structure having a first insulating layer, a semiconductor layer, and a second insulating layer stacked in this order in a first direction, the first structure extending in a second direction, memory cells provided on a surface of the semiconductor layer facing in a third direction, and connected in series in the second direction, and a third insulating layer contacting at least one of first and second end portions of the first structure in the second direction and not covering at least a part of an area between the first and second end portions. A lattice spacing of semiconductor atoms in the semiconductor layer in the second direction is larger than a lattice spacing of the semiconductor atoms in the semiconductor layer in the first direction.

Abstract: The present invention provides a transistor having a high on-state current. The transistor includes a plurality of fins, a first oxide semiconductor, a gate insulating film, and a gate electrode. One of adjacent two fins includes a second oxide semiconductor and a third oxide semiconductor. The other includes a fourth oxide semiconductor and the third oxide semiconductor. The second oxide semiconductor and the fourth oxide semiconductor include regions that face each other with the gate electrode positioned therebetween. The gate electrode and the second oxide semiconductor overlap with each other with the gate insulating film and the first oxide semiconductor positioned therebetween. The gate electrode and the fourth oxide semiconductor overlap with each other with the gate insulating film and the first oxide semiconductor positioned therebetween.

Abstract: A magnetoresistive element according to an embodiment includes: a first magnetic layer; a second magnetic layer; a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a third magnetic layer disposed between the first magnetic layer and the first nonmagnetic layer; and a layer having an amorphous structure, the layer containing two or more elements that are contained in the first magnetic layer, the layer being disposed between the first magnetic layer and the third magnetic layer.

Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.

Abstract: A magnetic cell core includes at least one stressor structure proximate to a magnetic region (e.g., a free region or a fixed region). The magnetic region may be formed of a magnetic material exhibiting magnetostriction. During switching, the stressor structure may be subjected to a programming current passing through the magnetic cell core. In response to the current, the stressor structure may alter in size. Due to the size change, the stressor structure may exert a stress upon the magnetic region and, thereby, alter its magnetic anisotropy. In some embodiments, the MA strength of the magnetic region may be lowered during switching so that a lower programming current may be used to switch the magnetic orientation of the free region. In some embodiments, multiple stressor structures may be included in the magnetic cell core. Methods of fabrication and operation and related device structures and systems are also disclosed.

Abstract: Disclosed is a solid state memory having a non-linear current-voltage (I-V) response. By way of example, the solid state memory can be used as a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the nonvolatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

Abstract: A semiconductor memory device includes string select lines extending in a first direction, vertical pillars connected to the string select lines, sub-interconnections on the string select lines, bitlines connected to the vertical pillars through the sub-interconnections, and upper contact plugs connecting the sub-interconnections to the bitlines. The string select lines include odd and even string select lines alternately arranged in a second direction. The sub-interconnections each connect a pair of vertical pillars respectively connected to one of the odd string select lines and one of the even string select lines that are adjacent to each other. Each of the upper contact plugs is between one of the sub-interconnections and one of the bitlines. Each of the upper contact plugs is arranged more adjacent to one string select line of the adjacent string select lines to which the pair of vertical pillars connected by the sub-interconnections are connected.

Abstract: Electronic devices have a semiconductor memory unit including a magnetization compensation layer in a contact plug. One implementation of the semiconductor memory unit includes a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer, and a contact plug arranged in at least one side of the variable resistance element and comprising a magnetization compensation layer. Another implementation includes a variable resistance element having a stacked structure of a first magnetic layer having a variable magnetization, a tunnel barrier layer, and a second magnetic layer having a pinned magnetization; and a contact plug arranged at one side of and separated from the variable resistance element to include a magnetization compensation layer that produces a magnetic field to reduce an influence of a magnetic field of the second magnetic layer on the first magnetic layer.

Abstract: A memory structure and a manufacturing method thereof are provided. The memory structure includes a bottom oxide layer, a first conductive layer on the bottom oxide layer, a first insulation recess, a plurality of insulating layers on the first conductive layer, a plurality of second conductive layers, a second insulation recess, a channel layer on a sidewall of the second insulation recess, and a memory layer located between the channel layer and the second conductive layers. The first insulation recess has a first width and penetrates through the first conductive layer. The second conductive layers and the insulating layers are interlacedly stacked, and the second conductive layers are electrically isolated from the first conductive layer. The second insulation recess located on the first insulation recess has a second width larger than the first width and penetrates through the insulating layers and the second conductive layers.

Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein.

Abstract: Spin-transport elements using semiconductors have had the problem of higher element resistance than conventional GMR elements and TMR elements, making it difficult to obtain high magnetoresistance ratios. A magnetoresistive element including a semiconductor channel layer; a first ferromagnetic layer disposed on the semiconductor channel layer; a second ferromagnetic layer disposed away from the first ferromagnetic layer; and a non-magnetic first reference electrode disposed away from the first ferromagnetic layer and the second ferromagnetic layer, wherein current is input from the second ferromagnetic layer to the first ferromagnetic layer through the semiconductor channel layer, a voltage between the second ferromagnetic layer and the first reference electrode is output.

Abstract: A storage element includes a storage layer, a fixed magnetization layer, a spin barrier layer, and a spin absorption layer. The storage layer stores information based on a magnetization state of a magnetic material. The fixed magnetization layer is provided for the storage layer through a tunnel insulating layer. The spin barrier layer suppresses diffusion of spin-polarized electrons and is provided on the side of the storage layer opposite the fixed magnetization layer. The spin absorption layer is formed of a nonmagnetic metal layer causing spin pumping and provided on the side of the spin barrier layer opposite the storage layer. A direction of magnetization in the storage layer is changed by passing current in a layering direction to inject spin-polarized electrons so that information is recorded in the storage layer and the spin barrier layer includes at least a material selected from oxides, nitrides, and fluorides.

Abstract: Apparatuses and methods for sensing a resistance variable memory cell include circuitry to apply a programming signal to a memory cell in the array, the programming signal associated with programming resistance variable memory cells to a particular data state, and detect a change in resistance of the memory cell to determine if a data state of the memory cell changes from an initial data state to a different data state during application of the programming signal.

Abstract: Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a dielectric stack of alternating dielectric materials and at least one conductive via extending through the dielectric stack. Semiconductor devices including a vertical memory block include at least one vertical memory block, which includes slots extending between adjacent memory cells of a three-dimensional array. The slots are separated by a first distance in a first portion of the block, and by a second, greater distance in a second portion of the block. Methods of forming vertical memory blocks include forming slots separated by a first distance in a memory array region and by a second, greater distance in a via region. At least one conductive via is formed through a stack of alternating first and second dielectric materials in the via region.