Patents Examined by Alonzo Chambliss
  • Patent number: 11862538
    Abstract: In some examples a semiconductor chip package includes a conductive terminal. In addition, the semiconductor chip package includes a die pad including a top side and a recess extending into the top side. The die pad is downset relative to the conductive terminal. Further, the semiconductor ship package includes a semiconductor die positioned within the recess, wherein the semiconductor die has an outer perimeter, and a solder fillet engaged within the recess and with the outer perimeter of the semiconductor die. Still further, the semiconductor chip package includes a wire bond coupled to the semiconductor die and the conductive terminal, and a mold compound covering the conductive terminal, the wire bond, the die pad, and the semiconductor die.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chung-Hao Lin, Hung-Yu Chou, Bo-Hsun Pan, Dong-Ren Peng, Pi-Chiang Huang, Yuh-Harng Chien
  • Patent number: 11854918
    Abstract: A semiconductor package includes a first die. The first die has a first side and a second side different from the first side and includes a first seal ring. The first seal ring includes a first portion at the first side and a second portion at the second side, and a width of the first portion is smaller than a width of the second portion.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Chih-Chia Hu
  • Patent number: 11854949
    Abstract: The present invention provides a package structure and a method for manufacturing the same. The package structure includes at least two electrical elements, a second reconstruction layer, and a metal lead frame, wherein at least one of the electrical elements is a chip, at least one of the electrical elements has a first reconstruction layer, and the second reconstruction layer has a smaller pin pitch than that of the metal lead frame; the second reconstruction layer has a first surface and a second surface, a functional surface of the electrical element is disposed on and connected to the first surface, and at least one of the electrical elements is connected to the second reconstruction layer; and the second surface is disposed on and connected to the metal lead frame. A fan-out package structure is formed on the metal lead frame, which improves the heat dissipation capacity of the chip.
    Type: Grant
    Filed: November 20, 2021
    Date of Patent: December 26, 2023
    Assignee: JCET GROUP CO., LTD.
    Inventors: Yaojian Lin, Danfeng Yang, Shuo Liu, Chenye He
  • Patent number: 11848280
    Abstract: An assembly structure and a method for manufacturing the same are provided. The method for manufacturing the assembly structure includes providing a substrate defining an active region and a side rail surrounding the active region; and forming a frame structure on the side rail.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: December 19, 2023
    Assignee: ADVANCED SEMlCONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yu-Ju Liao
  • Patent number: 11848409
    Abstract: A display device includes a substrate including a display area and a non-display area, a pixel located in the display area, a pad unit on one side of the non-display area, and a driver connected to the pixel. The pixel includes a first insulating layer, a first light emitting element on the first insulating layer, a second insulating layer on the first light emitting element and exposing one end portion and another end portion of the first light emitting element, a first contact electrode on the second insulating layer and connected to the one end portion of the first light emitting element, and a second contact electrode on the second insulating layer and connected to the other end portion of the first light emitting element. The pad unit includes a pad metal layer, a first pad insulating layer, a second pad insulating layer, and a pad electrode.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: December 19, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin Yeong Kim, Mi Jin Park, Sang Ho Park, Tae Hoon Yang, Sung Jin Lee
  • Patent number: 11837530
    Abstract: A lead frame includes: a support portion having a through-hole formed in as end; a lead; and a heat dissipation plate welded with the support portion in one opening of the through-hole. A manufacturing method of a lead frame includes: shaping a frame member from a metal plate, the frame member including a support portion having a through-hole formed in an end, and a lead; and welding a heat dissipation plate with the support portion in one opening of the through hole.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: December 5, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Jun Izuoka, Koichi Ishida, Mitsuori Yoshimi
  • Patent number: 11837549
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: December 5, 2023
    Assignee: Intel Corporation
    Inventors: Kemal Aygun, Zhiguo Qian, Jianyong Xie
  • Patent number: 11830792
    Abstract: The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: November 28, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Kentaro Nasu
  • Patent number: 11824005
    Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Patent number: 11823991
    Abstract: A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hung Chen, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11817374
    Abstract: A packaged electronic device has a package structure, first leads, second leads and a tie bar. The package structure has a first side, a second side, a third side, a fourth side, a fifth side and a sixth side, the second side spaced from the first side along a first direction, the fourth side spaced from the third side along an orthogonal second direction, and the sixth side spaced from the fifth side along an orthogonal third direction. The first leads extend outward in a first plane of the second and third directions from respective portions of the third side, the second leads extend outward in the first plane from respective portions of the fourth side, and the tie bar is exposed along the fifth side in a second plane of the second and third directions, the second plane between the first plane and the first side.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: November 14, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Chih-Chien Ho, Bo-Hsun Pan, Yuh-Harng Chien
  • Patent number: 11817391
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventors: Kemal Aygun, Zhiguo Qian, Jianyong Xie
  • Patent number: 11817429
    Abstract: A semiconductor device includes: multiple semiconductor elements each having a one surface and a rear surface in a plate thickness direction; a first member that sandwiches the multiple semiconductor elements and is electrically connected to an electrode on the one surface; a second member electrically connected to an electrode on the rear surface; and multiple terminals that are continuous from the first or second member. An area of the second member is smaller than that of the first member. Semiconductor elements are arranged in a longitudinal direction of the second member. The semiconductor device further includes a first joint portion that electrically connects each semiconductor element and the second member and a second joint portion that electrically connects a terminal and the second member. The multiple solder joint portions are symmetrically placed.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: November 14, 2023
    Assignee: DENSO CORPORATION
    Inventors: Noriyuki Kakimoto, Hiroshi Ishino, Shinji Hiramitsu
  • Patent number: 11810892
    Abstract: A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: November 7, 2023
    Assignee: IMEC vzw
    Inventors: Jaber Derakhshandeh, Eric Beyne, Gerald Peter Beyer
  • Patent number: 11798869
    Abstract: A semiconductor package includes: a plurality of die pads; a plurality of semiconductor chips provided on the plurality of die pads respectively; a plurality of lead terminals connected to the plurality of semiconductor chips respectively; and a package sealing the plurality of die pads, the plurality of semiconductor chips, and the plurality of lead terminals, the plurality of die pads and the plurality of lead terminals are exposed from a lower surface of the package, and on the lower surface of the package, grooves are provided among the die pads adjacent to one another and among the lead terminals adjacent to one another.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: October 24, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuki Terado, Shiori Uota, Shinji Sakai
  • Patent number: 11799060
    Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: October 24, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Cheng-Lin Lu, Chih-Hao Chen, Chi-Shiang Hsu, I-Lun Ma, Meng-Hsiang Hong, Hsin-Ying Wang, Kuo-Ching Hung, Yi-Hung Lin
  • Patent number: 11798925
    Abstract: A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chia Lai, Cheng-Chieh Hsieh, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11791169
    Abstract: A method for fabricating an electronic device includes providing an encapsulant having an encapsulation material, providing a first laser beam and forming a trench into a main surface of the encapsulant by removing the encapsulation material by means of the first laser beam, forming a mask along a portion above the edge of the trench, and providing a second laser beam and sweeping the second laser beam over a surface area of the main surface of the encapsulant, wherein the surface area covers at least an area spatially confined by the trench.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: October 17, 2023
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Pei Luan Pok, Roslie Saini bin Bakar, Chau Fatt Chiang, Chee Hong Lee, Swee Kah Lee, Yu Shien Leong, Jan Sing Loh, Yean Seng Ng
  • Patent number: 11784124
    Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Chia-Wei Tu
  • Patent number: 11784157
    Abstract: A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: October 10, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Li-Sheng Weng, Charles David Paynter, Ryan Lane, Jianwen Xu, William Stone