Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: Blocks of data are transferred in burst mode from a first device attached to a first bus, to a second device attached to a second bus having time multiplexed address/data lines. A bridge circuit includes an address register, which is coupled to the first bus, a circuit for incrementing the address register, and an output register coupled to the address/data lines of the second bus. In an aborted burst mode transfer of a block of data from one device to the other in which a "last" data byte in the block was successfully transferred, but a "next" byte of data was not successfully transferred, the system provides for an efficient retry of the transfer of the aborted data block. This efficient retry is accomplished in part by swapping the information in the address register of the bridge circuit with the information in its output register, such that the output register contains the address of the "next" data byte.

Abstract: A process for monitoring the acknowledgement of a request to execute a command script (script) through a non-guaranteed protocol (S.N.M.P.), in an information system (SI) in a network (RE) comprising a manager (GE) and agents (AG1) for executing commands, wherein the manager first sends the agent in charge of executing the command script a ticket request using a command (Get mrsGetTK) of the "get" type, and the agent returns (GetResponse) a ticket to the manager, the manager then sends the execution request to the agent using a command (Set mrsExecute cmd TK) of the "set" type, for which the ticket it a parameter, then the agent verifies the validity of the request and creates an instance for the execution of the command associated with the ticket and the manager then verifies proper reception of the request by scanning (Get mrsStatus) the instance using the agent. The instant invention is particularly applicable to heterogeneous information systems.

Abstract: A computer system includes a bus arbiter for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of programmable registers are provided to receive configuration information for controlling the relative priority given to each of the bus masters when bus request contention occurs. One or more of the bus masters is configured to generate a grading signal following a particular bus transaction to indicate whether the latency in obtaining the bus during the previous bus request phase was generous, was acceptable, or was longer than desired (i.e., the latency requirement for the device was either violated or reached a critical or near-critical point).

Abstract: A method and apparatus for monitoring the status of a computer network by displaying polygon-shaped objects (or "icons") to represent groups of devices connected to the network. In a preferred embodiment each device (or "node") on the network is assigned to one of a number of groups (or "clusters"), each cluster is represented as a polygon-shaped object on a computer system display, and the number of sides for each polygon is displayed according to the size of the group represented. The appearance of the sides of each polygon may also help indicate the size of the group. A base value may be varied to partly govern the shape and appearance of the polygon.

Abstract: A bypass mechanism in a vector computer is disclosed. The vector register bypasses data to be written in the inner registers from input or output of the write data register. The bypass mechanism is mainly realized by a selector and a decoder. The selector selects any one of data to be written in the registers at the timing before 2 cycles, data to be written in the registers at the timing before 1 cycle, and the read data from the registers. The decoder controls the selector according to a mask signal from the mask register; a signal of a timing which is before one cycle of the mask signal, and a bypass signal from said controller.

Abstract: A router includes a routing table containing flags each representing a public-network side or a LAN side. A path for a received packet is determined such that the packet is forwarded to the next node through the LAN according to the next node address when the flag corresponding to the specified destination represents the LAN side, and the packet is forwarded to the next node through the public network according to the next node address when the flag represents the public network side. When a change of the routing information sets is monitored, the routing table is searched for the second router having the flag representing the public network side and then the changed routing information sets are transmitted to the second router.

Abstract: This document describes a feature that can be added to existing pipelined architectures (such as RISC) to enhance packet based or message passing communications. The feature integrates the communication interface directly into the pipeline of the processor, offering the potential to greatly reduce latency and overhead for fine grain communications. Additionally, a second interface is provided to maintain high bandwidth for large blocks of data.

Abstract: A power conservation system for use in a computer system. The power system has an activity monitor and a plurality of power modes of operation. The activity monitor detects the activity level of the computer system through hardware and/or software. By controlling the power mode of operation in response to the activity of the computer system, the power consumption of the computer system can be controlled.

Abstract: An interactive trade network is described that integrates distributive messaging using a host computer and telecommunication networks, real-time interactive communications, a hierarchical knowledge matrix containing two familiar and comprehensive indices of classes of goods and classes of establishments and a legend of trade-related, cross-reference terms or parameters, a multiline programmable application, an integrated application program interface, and integrated application programs. The Host System uses each Index Number of each of the indices as a topic board name. The apparatus creates a highly-selective media for either (a) messaging on mutually exclusive indexed topics of trade or (b) engaging in pubic or private real-time conferencing or electronic mail dedicated to any class of indexed economic activity. It enables progressive discussions on, and the retrieval of just the information needed under, discrete indexed topics on trade instantaneously.

Abstract: An address management circuit and method of operation, for use in a communications internetworking device, includes a search engine having first and second search circuits for concurrently searching a network address table for source and destination addresses of a frame received by the communications internetworking device. Memory read cycles of the source and destination address searches are interleaved to allow a memory access to occur during every system cycle to thereby rapidly complete the searches for both the source and destination addresses.

Abstract: A system and method is provide for managing input/output (I/O) resources in a computer system. The system includes a hardware resource manager which tracks the use of the I/O resources. In addition, the hardware resource manager can allocate the resources between device drivers and provide a standard implementation to be used by device drivers.

Abstract: A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.

Abstract: Systems are provided for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition. One embodiment concerns a latch feedback assembly, such as a SRL, which includes multiple series-connected latches having a feedback connection between last and first latches. The latches are clocked to temporarily reserve a delayed backup copy of data from the first latch on the last latch. Upon detection of an exception, the backup copy is first preserved by disabling writes to the last latch; then the backup copy is copied to the first latch to restore the first latch to its state prior to occurrence of the exception. Another embodiment involves a register file save/restore mechanism, in which an additional bank of registers, called a "backup register", is coupled to a register file. When data is stored in an address of the register file, the address and its data content are also stored in the backup register.

Abstract: A peripheral device, connected to an address bus, which has yet to be assigned an I/O address has a pin connected to a configuration select output of a control logic circuit (or a CPU). The peripheral device is reset upon start-up of the system and is not yet required to respond to normal bus accesses or traffic. The CPU analyzes the available addresses in the address space and selects an available I/O address for assignment to that peripheral device. In one embodiment, the CPU then sends a serial bit stream containing the selected I/O address to that peripheral device over a configuration select line. In another embodiment, the CPU asserts a configuration select signal to the peripheral device. The CPU then transmits the selected I/O address to the peripheral device on the address bus. The transmitted I/O address is then stored in the peripheral device, and the device will now respond to this I/O address during subsequent operation of the system.

Abstract: When a register whose content is not determined because a preceding arithmetic operation is still being executed is to be referred to by the following instruction word, or when the following instruction word uses an arithmetic operator unit which is still executing a preceding arithmetic operation, execution of the following instruction word is suspended until the preceding arithmetic operation is completed. Otherwise, even when the arithmetic operation of the preceding instruction word is being executed, control is made to execute the following instruction word without waiting for completion of the preceding arithmetic operation, thereby maximally utilizing parallel processing power.

Abstract: The present invention provides interprocess communication in a DBMS. The present invention provides the ability for these processes to communicate with other DBMS processes or processes external to the DBMS. A pipe is implemented as an object of the general purpose object cache. The general purpose object cache resides in the systems shared memory space. It is concurrently accessible by many sessions, or processes. A pipe is located in a shared global memory area. The present invention provides the ability to send a message (i.e., record) to a pipe, and receive a message (i.e., record) from a pipe. A pipe is located in shared memory. Shared memory can contain multiple pipes. Each pipe is comprised of a linked list of records, and linked list of sessions, an exclusivity indicator, and a session waiting indicator. Multiple sessions can access the same pipe, and each pipe can contain multiple messages. A message is sent by a sending session to a local buffer. The contents of the local buffer is sent to a pipe.

Abstract: A special memory overlay circuit uses a first DRAM buffer memory in combination with a second faster SRAM buffer memory to reduce the time required to translate information into different network protocols. Packet data is stored in the DRAM buffer memory and packet headers requiring manipulation are stored in the SRAM buffer memory. Because the SRAM has a faster data access time than the DRAM buffer memory, a processor can reformat the packet header into different network protocols in a shorter amount of time. Packet headers also use a relatively small amount of memory compared to remaining packet data. Since the SRAM buffer memory is only used for storing packet headers, relatively little additional cost is required to utilize the faster SRAM memory while substantially increasing network performance.

Abstract: The present invention relates to a computer system and more particularly to a computer system which allows option controller cards for various input/output (I/O) devices to be added on the motherboard at minimum cost.

Abstract: An instruction for returning to a ROM is written to a position where data is not broken even if a next correction is executed in order not to the content of a register even if an interruption processing for correction and a processing for returning a ROM program are executed. A microcomputer connected through a serial i/O bus, an EEROM, and a correction data writing device comprises a CPU, a RAM, a ROM, a PC comparison register section, a ROM correction processing circuit having a PC value latch section, and a serial i/O section. The CPU sequentially executes an internal sequence control of the microcomputer and a logical operation in accordance with instructions written in the ROM as a program in advance. The RAM temporarily saves intermediate processing data of, e.g. calculation, or saves an adjustment value transferred from the EEPROM when the program is actually executed.