Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A method and an apparatus for confirming matching of data in a distributed processing system aiming easy maintenance of the matching of the data and efficient parallel design work in a distributed processing system. In the distributed processing system having a server including a database and plural clients utilizing data in the database, said server and clients are connected to each other. The server stores information of destinations to which data in the database has been distributed and receives information of an editorial history of the data from a client that is a destination of the distributed data to store the editorial history information at the destination client on the side of the server. After that, matching of the data is confirmed on the side of another client on the basis of the distributed data's destination information or the editorial history information stored in the server.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A firewall isolates computer and network resources inside the firewall from networks, computers and computer applications outside the firewall. Typically, the inside resources could be privately owned databases and local area networks (LAN's), and outside objects could include individuals and computer applications operating through public communication networks such as the Internet. Usually, a firewall allows for an inside user or object to originate connection to an outside object or network, but does not allow for connections to be generated in the reverse direction; i.e. from outside in. The disclosed invention provides a special "tunneling" mechanism, operating on both sides of a firewall, for establishing such "outside in" connections when they are requested by certain "trusted" individuals or objects or applications outside the firewall.

Abstract: Described herein is a distributed computer system having a plurality of computer nodes arranged logically adjacent to each other in a communications ring. Each computer node receives communications from a preceding computer node and sends communications to a succeeding computer node. The computer nodes maintain individual local clocks with local time values c. The clocks are synchronized to each other through a sequence of distributed processing steps. The steps include a step of measuring an approximate local offset d of the local time value of each computer node relative to the local time value of a logically adjacent computer node in the communications ring. A subsequent step includes passing a plurality of collation variables from a lead computer node, through the computer nodes forming the communications ring, and back to the lead computer node in a single pass. The collation variables are processed at each computer node as they are passed around the communications ring.

Abstract: Multiple banks associated with a multiple set associative cache are stored in a single chip, reducing the number of SRAMs required. Certain status information for the second level (L2) cache is stored with the status information of the first level cache. This enhances the speed of operations by avoiding a status look-up and modification in the L2 cache during a write operation. In addition, the L2 cache tag address and status bits are stored in a portion of one bank of the L2 data RAMs, further reducing the number of SRAMs required. Finally, the present invention also provides local read-write storage for use by the processor by reserving a number of L2 cache lines.

Abstract: A microprocessor includes a control register having a predetermined bit which is unconditionally writable to either a first state or a second state. Additional bits of the control register are writable to either the first or second state when the predetermined bit has the first state. Each additional bit is not writable when the predetermined bit has the second state. The microprocessor further includes at least one circuit controlled by the state of a corresponding one of the additional bits of the control register. The writability of the additional bits is preferably further conditioned upon the state of a machine status register, which is unconditionally writable to either the first state or the second state. A primary AND gate and a secondary AND gate corresponding to each additional bit control the writability of the additional bits.

Abstract: In a parallel processor system, each processor is connected to a secondary memory. A main memory of a sender processor has first small buffers and a main memory of a receiver processor has second small buffers. The sender processor divides data correspondingly to destinations and transmits the data to receiver processors through the first small buffers. Each receiver processor further divides the received data, stores the divided data in a bucket storage region in the secondary memory, and performs a designated process. Since data is divided in two stages, with a very reduced number of small buffers, bucket tuning process can be performed.

Abstract: A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory includes first, second and third memory banks connected to the core processor by first, second and third data and address buses, respectively. The core processor includes a program sequencer and first and second computation blocks for performing first and second subsets, respectively, of the digital signal computations. Single, dual or quad data words of 32 bits each may be accessed in each of the memory banks during each clock cycle. The multiple data words may be transferred to one or both of the first and second computation blocks.

Abstract: A power conservation system for use in a computer system. The power system has an activity monitor and a plurality of modes of operation. The activity monitor can place the computer system in a reduced power consumption state during periods of low activity without waiting for a period of complete inactivity. By controlling the power mode in response to the activity of the computer system, the power consumption of the computer system can be controlled.

Abstract: A system capable of granting Internet access to users when direct connection to their usual home Internet Service Providers (ISPs) is impossible, impractical or prohibitively expensive. The system offers users a unified method of login to other independent ISPs to provide easy and inexpensive access to the Internet and its various services. The system validates user logins, generates billing data, provides usage time and monitors communication links. The system also isolates the shells of the servers of the ISPs from the user until such time as the user has been determined to be valid, thereby providing security to the ISPs against unauthorized access to their servers. The system performs these tasks while requiring only a small amount of communication bandwidth for communication monitoring and billing.

Abstract: A method and system within a data processing system are disclosed for halting execution of instructions by a processor in response to an enumerated occurrence of a selected combination of internal states within the processor. The processor includes a number of state machines and a means for monitoring the states of the number of state machines. According to the present invention, a selected combination of states of a subset of the state machines is specified. An enumerated occurrence of the selected combination of states of the subset of the state machines is then detected. In response to the enumerated occurrence of the selected combination of states, execution of instructions by the processor is halted such that states of the number of state machines within the processor remain substantially unchanged following the enumerated occurrence of the selected combination of states.

Abstract: A data processing system (20) having programmable chip select signal negation. A user programmable "NEGATE EARLY" value generates a chip select negation one bus cycle before the end of a transaction, giving an external device additional time to disconnect from the current bus cycle before the start of the next bus cycle. Early negation of a chip select signal provides an efficient method of interface with slower devices while providing adding functionality to the chip select signal.

Abstract: The invention relates to exchangeable memory or PC-cards with several integrated circuits for personal computers. These PC-cards are used as a large capacity mass memory for replacing floppy disks and other exchangeable magnetic supports. To protect the content of these PC-cards against unauthorized use, the invention proposes the incorporation into the card (CC) of a specific security integrated circuit chip (MPS), which performs a clearance function for access to the memory chips (MEM). A microcontroller (MPC) also placed in the card comnunicates with the computer and with the security circuit. It makes the security chip validate a confidential code introduced from the computer, whilst also supplying memory chip control signals as a function of the validation result.

Abstract: Systems are provided for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition. One embodiment concerns a latch feedback assembly, such as a SRL, which includes multiple series-connected latches having a feedback connection between last and first latches. The latches are clocked to temporarily reserve a delayed backup copy of data from the first latch on the last latch. Upon detection of an exception, the backup copy is first preserved by disabling writes to the last latch; then the backup copy is copied to the first latch to restore the first latch to its state prior to occurrence of the exception. Another embodiment involves a register file save/restore mechanism, in which an additional bank of registers, called a "backup register", is coupled to a register file. When data is stored in an address of the register file, the address and its data content are also stored in the backup register.

Abstract: A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor.

Abstract: A general dimensioning method and system for allocating limited transmission resources to various virtual paths defined on top of a physical network. A two-level hierarchical structure is defined with a layer of one or more virtual paths on top of a layer of physical network elements. Traffic demand is specified for each virtual path and the Entropy Rate Function is used as a blocking measure. The loads on the various links are balanced by equalizing blocking probabilities and the optimal allocation of network physical resources is determined.

Abstract: An instruction executing section supplies an instruction of a certain context to a pipeline and executes the context. When a vacancy of the pipeline is judged, the instruction executing section switches the context to another context which is being executed, thereby simultaneously executing a plurality of contexts. An ID setting section sets a peculiar context ID to each of the plurality of contexts which are simultaneously executed by the instruction executing section. A register renaming section executes a multi-renaming such that a register name which is used when the plurality of contexts are simultaneously executed by the instruction executing section is renamed to a register name CIDi-Rj obtained by adding a designation register name Rj (j=1, 2, 3, . . . , m) of an execution instruction to CIDi as a context ID which was set by an ID setting section and whose context is being executed and the physical register is allocated.

Abstract: A computer device for receiving and utilizing a radio card. The radio transceiver is self contained inside the radio card and has antenna contacts disposed on the radio card on one end and an electrical interface on the other. The computer device receives the radio card such that it engages the electrical interface. The computer device additionally has and cap which covers the opening into which the radio has been inserted. Antenna contacts are disposed on the cap to engage the antenna contacts on the radio card. At least one antenna is operably connected to the radio card through the cap. A band is used to attach the cap to the housing of the computer device. The antenna or antennas are embedded in the cap, in the band, or embedded in or attached to the housing of the computer device. Positioning two similar antennas in different position creates an antenna diversity scheme. Shielding can be added to the cap to help reduce the escape of electronic noise.