Abstract: An array substrate, includes: a substrate, three metal layers stacked on the substrate, and a plurality of signal line leads disposed in a peripheral area of the array substrate. The plurality of signal line leads are distributed in at least two of the three metal layers.

Abstract: An array substrate, manufacturing method thereof, and a display device according to some arrangements of the present disclosure include: a first transistor and a second transistor; an active layer of the second transistor is disposed on a side of the interlayer dielectric layer of the first transistor away from the substrate; an insulating layer is disposed between the interlayer dielectric layer of the first transistor and the active layer of the second transistor, and the insulating layer has an ability to block hydrogen.

Abstract: The present disclosure provides a demultiplexer, an array substrate and a display device. The array substrate comprises a plurality of data line leads, a plurality of data lines arranged side by side and the demultiplexer. The demultiplexer includes first to third control gate lines arranged in parallel and first to sixth thin film transistors. The first thin film transistor to the third thin film transistor are positioned at a side of the demultiplexer proximal to the first control gate line, the fourth thin film transistor to the sixth thin film transistor are positioned at a side of the demultiplexer proximal to the third control gate line, and drains of the first thin film transistor to the sixth thin film transistor are respectively coupled to corresponding ones of the plurality of data lines.

Abstract: A chip on film package including a flexible film, a first patterned circuit layer, one or more first chips, a second patterned circuit layer, and one or more second chips. The flexible film includes a first surface and a second surface opposite to the first surface. The first patterned circuit layer is disposed on the first surface. The one or more first chips are mounted on the first surface and electrically connected to the first patterned circuit layer. The second patterned circuit layer is disposed on the second surface. The one or more second chips are mounted on the second surface and electrically connected to the second patterned circuit layer.