Abstract: A hard disk controller integrated circuit of a SCSI target device comprises a sequencer which causes a SCSI bus to transition from a command bus phase to a data transfer bus phase during execution of an autoread or an autowrite SCSI command without waiting for a communication from a microprocessor of the SCSI target device. In some embodiments, the command is determined to be either an autotransfer command or a non-autotransfer command. If the command is a non-autotransfer command, then the sequencer does not proceed directly to the data transfer phase but rather requires microprocessor intervention before proceeding to the data transfer phase. In some embodiments, an autotransfer command (such as an autoread or an autowrite command) is carried out by the disk drive controller integrated circuit with only two interrupts being generated to the microprocessor: one after receiving the autotransfer command from the initiator; and one after data transfer of the autotransfer command is complete.

Abstract: An interface apparatus, built in a microcomputer, and capable of reducing the load on a CPIU by including a function to judge by itself, when data is received from the outside, whether it is necessary for the received data to generate an interruption request so as to make the (CPU execute the processing, thereby avoiding the generation of an unnecessary interruption request. The interface apparatus is provided with a receiving register 3 which stores data received newly, a buffer register 4 which stores data received precedingly, a table 5 which stores data designated beforehand, and a comparing circuit 6 which compares the data stored in them with each other to make an interruption control register 7 generate an interruption request signal INT only when the comparison results do not show coincidence.

Abstract: A virtual field programmable gate array device (20) includes a plurality of processors (22), each containing a central processing unit (24), memory (34), and a network interface (26). Each processor (22) may be programmed to emulate a multiple number of gates of a conventional field programmable gate array device. Each processor (22) is part of a network array to allow for information transfer between and among each processor (22). Information transfer is accomplished through the use of delivery units (50) that identify the routing vector for the information to an appropriate processor (22).

Abstract: A distributed direct memory access (DMA) architecture where DMA controllers are modified to create isolated DMA channels. Each isolated channel includes its own set of uniquely addressable registers which provide functional compatibility with conventional DMA controllers. A DMA master interacts compatibly with the computer system and transparently communicates special cycles to the isolated DMA channels to cause the distributed DMA architecture to appear as the DMA controllers. The DMA master spawns special cycles to the isolated channels for sharing common write data with multiple channels and merging read data into a single DMA controller compatible register. Channel 4 cascading is also handled via tracking registers and special cycles to maintain disable and masking functionality of channel 4 as it effects channels 0-3.

Abstract: A bi-directional digital signal processing system comprises: a memory including a memory buffer of a predetermined size; a CODEC unit; and a bi-directional digital signal interface. The interface is adapted to be coupled to the memory and the CODEC and is further adapted to at least bi-directionally transfer digital signal samples from and to one selected memory location in the memory buffer.

Abstract: A multiplexed synchronous/asynchronous data bus uses three communications lines (T, C, R) to convey bi-directional synchronous data between two data devices at a relatively low data transfer rate. The data bus is configured as a full-duplex asynchronous data bus by communicating a false address between the two data devices on two communications lines (T, C) using the synchronous data bus, holding the two communications lines (T, C) in a logic high state for a period of time, and continuing to hold one of the two communications lines (C) in the logic high state during full-duplex asynchronous communication. Full-duplex asynchronous data can then communicated between the two data devices at a higher data transfer rate on two of the three communications lines (T, R).

Abstract: Disclosed are apparatus and methods for synchronized presentation of analog and digital data by applying a common synchronization scheme to both types of data. Digital data is "streamed" by transferring the data in blocks from a source to a series of memory buffers, where it accumulates for subsequent transfer to an output device driver. The control module responsible for data streaming periodically reports a temporal location within the presentation represented by the data. A supervisory module designates one of the control modules a "master", and periodically compares the values reported by the various other control modules against that reported by the master. If a comparison exceeds a threshold tolerance value associated with each control module, a sync pulse is delivered to that control module, causing it to correct the synchronization mismatch.

Abstract: A parallel input/serial output device for inputting code bits in parallel and outputting the same in serial in a variable-length encoder divides a bit word into one with a sign bit and without a sign bit in a table for a variable-length encoder, sequentially stores the absolute values in the table in case of the bit word with a sign bit, sequentially stores the remaining bits with the most significant bit being stored finally in case of those with a sign bit, sequentially outputs bits from the next one of the most significant bit in serial and outputs the most significant bit as the last bit if the counted value becomes one. Therefore, the size of an internal conversion table can be decreased to a half, thereby reducing the number of used elements. Accordingly, the size of an address decoder can be reduced to a half and the operational speed can be improved.

Abstract: An apparatus for synchronizing data retrieval is described. The apparatus comprises a storage media storing data, a storage control device coupled to the storage media for retrieving the data from the storage media, memory coupled to the storage control device for storing the data; and a scheduling unit coupled to the memory for scheduling retrieval of the data from the storage media before a specified time. A storage media for storing computer instructions is also described.

Abstract: The present invention teaches a new system for transferring data between a network and hosts coupled to the network. The system uses an adapter, that is coupled between the host and the network, to allow segmenting and reassembling cells directly in the host memory. The present invention also teaches a pipelined DMA architecture to overcome the problem of the interruption of the DMA operation when switching from one virtual circuit to the next. This architecture depends on fast access to a local memory used for storing buffer descriptors for each virtual circuit. In this architecture, a two stage pipeline is used with the first stage performing the local memory access while the second stage performs the DMA transfers. When the pipeline is filled, both stages will operate in parallel yielding significant gain in performance due to continuous operation of the DMA.

Abstract: A system for allowing a peripheral device to be inserted directly into a port of a computer system while the computer system is powered on. The insertion of a peripheral device into the computer system port is automatically detected, and a configuration operation is automatically performed when insertion of the peripheral device is detected. The system also allows a plurality of peripheral devices to be connected to a single port of a computer system by automatically determining the number of peripheral devices and assigning a unique address to each of the peripheral devices. The peripheral device may have a host port for communicating with the computer system, a slave port for connecting to a slave device, and a device manager which identifies if a slave device is connection.

Abstract: A system and method for providing annotation overlays from diverse sources of commentary for World-Wide Web documents is disclosed. Sources of commentary contribute annotation overlays regarding particular documents on the World-Wide Web. The annotation overlays from a particular source are stored on one or more overlay servers, which are connected to the Web. A user of a Web browser opens an annotation proxy server between the Web browser and the Web servers that intercepts all documents retrieved by the Web browser and merges with the retrieved documents commentary from sources designated by the user of the Web browser that refer to the requested documents. Multiple annotation overlay proxies can be serially connected. The annotation proxy can perform the merge operation by first creating a local annotation directory of annotation overlays from sources designated by the user then, when the user requests a document, merging with the requested document information only from the annotation directory.

Abstract: In a distributed computer system, an automated document annotation system and method adds hypertext cross-references to a set of known information sources into documents requested by a client computer in such a way that the merged document is displayable by existing Web browsers. The distributed computer network incorporates a plurality of servers to store documents. Each stored document has a unique document identifier and is viewable from a client computer having a browser configured to request and receive documents over the network. An annotation proxy, which is a software procedure configured to merge a requested document from a first server with hypertext links to documents containing associated supplemental information. The set of hypertext links and criteria for identifying where such links should be added to requested documents are defined by one or more dictionaries of cross-references.

Abstract: An audio data recording/reproducing method and apparatus for storing an index containing additional information and position information together with audio data in order to more easily manage the audio data. During reproduction of the audio data, using the stored index, the reproduction position is selected by a user and additional information can be utilized.

Abstract: A modular digital dictation system that can be easily modified to service a variable number of dictation stations and transcription stations. The modular digital dictation station comprises a central station for receiving digitized dictation signals from a network of dictation stations, storing the voice portion of the digitized dictation signals as digitized dictation segments, and routing the digitized dictation segments to a network of transcription stations. The central station includes a plurality of line interface and signal processing cards. The number of line interface and signal processing cards connected to the central station determines how many dictation stations and transcription stations the modular digital dictation station can service. The line interface cards may be removed from or connected to the central station during operations. A fast search program is provided to quickly find files containing desired digitized dictation segments stored in the central station.

Abstract: The present invention is an apparatus for adapting transmissions between an industry standard data bus of a host computer having a host memory and a fiber channel coupled between said host computer and a peripheral storage subsystem having at least one disk drive, which apparatus comprises an interface logic coupled between the industry standard bus and a local bus of the apparatus; a buffer memory coupled to the local bus; a multiplexor/control device coupled to the local bus and being disposed for transmitting therethrough address and data; a fiber channel controller disposed for formatting header and data structures that meet fiber channel protocol, which controller is coupled to the multiplexor/control; a gigabit link module disposed for converting the header and data structures from a parallel format to a serial format and being coupled between the fiber channel controller and the fiber channel; a microprocessor disposed for providing service requests from the host to read and write data from the host me

Abstract: A digital system which uses an arrangement of one or more parallel FIFO buffers in which each FIFO buffer handles data from only one application program at any time. In order to assure that no data written to a FIFO buffer by an application program will overflow the FIFO buffer, each FIFO buffer includes a flow control register which must be read by the processing unit running the application before writing data to an input/output device. The register stores a value which indicates the amount of space available in the FIFO buffer to which data may be written. Reading this register tells the application program how much data may be written without running the risk of overflowing the data storage area which the input/output device has available.

Abstract: A method and apparatus for providing a unified data approach to performing computational services, particularly in pen-based computer systems. The approach employs object oriented functions and establishes common data structures employable in the standardized form in particular defined functional domains of the computer system. The functional domains in which the common data structures are employable without adaptation include the view system, the scripting system, and the object store functional domains of the computational system, which preferably is a pen-based computer system. The apparatus according to the invention further includes an object system for creating, eliminating and managing the predetermined data objects and structures. The object store functional domain provides external storage with respect to the externally located operating system with which it cooperates through a minimal, i.e., narrow interface.

Abstract: A method is provided for controlling a plurality of electrical installations (A1-A3, B1-B4) of one or more types connected to a common data path (52), each including means for decoding a signal transmitted over this common data path to it by a single controller (50), comprising the steps of: transmitting, from each controlled installation to the single controller (50), an identification data frame, containing an installation type identifier code (b.sub.8 -b.sub.23); receiving of the identification data frame by the controller (50); decoding of the identification data frame by the controller (50); controlling of the installation (A1-A3, B1-B4) by the single controller according to a set of instructions (56, 57, 58) held in an instruction memory (55) of the single controller (50) and corresponding to the type of installation identified by the installation type identification code (b.sub.8 -b.sub.

Abstract: A data communications system (10) has a system management controller (100) and multiple data communications devices (21-1 through 21-n). The system management controller has a processor (110) and random access memory (115). The various data communications devices (21-1 through 21-n) are coupled to the system management controller (100) through a common address bus (12) and a common management bus (11). Through the processor (110), the system management controller (100) sequentially addresses each of the data communications devices (21-1 through 21-n) at a default data rate and determines a requested data rate for each device (FIG. 6, 305-333). The system management controller (100), through the processor (110), stores this requested data rate information, correlated with the address of each data communication device, in the random access memory (115) (FIG. 6, 305), and communicates with each such device at its requested data rate (FIG. 6, 335; FIG. 10, 500-545).