Patents Examined by Andres Munoz
  • Patent number: 10490740
    Abstract: A method of manufacture of a non-volatile memory system comprising: forming a dielectric layer having a hole; depositing a first electrode in the hole of the dielectric layer; applying an ion source layer over the first electrode; and depositing a second electrode over the ion source layer including: depositing an interface layer on the ion source layer, and applying a cap layer on the interface layer.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: November 26, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shuichiro Yasuda, Dale Collins, Scott E. Sills
  • Patent number: 10490652
    Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses semiconductor devices and manufacturing methods for the same. A semiconductor device may include: a substrate; a first active region on the substrate; a first gate structure positioned on the first active region; and a first source and a first drain that are positioned in the first active region and respectively on two sides of the first gate structure, where a size of the first drain is larger than a size of the first source. In forms of the present disclosure, because the size of the first drain is larger than the size of the first source, a current from the first drain to the first source is greater than a current from the first source to the first drain, so that the semiconductor device can make a read current relatively low and a write current relatively high in a static random access memory (SRAM), thereby improving a read margin and a write margin.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: November 26, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhenghao Gan, Junhong Feng
  • Patent number: 10490400
    Abstract: There is provided a technique that includes forming a nitride film on a pattern including a concave portion formed in a surface of a substrate by repeating a cycle. The cycle includes non-simultaneously performing: (a) forming a first layer by supplying a precursor gas to the substrate; (b) forming an NH-terminated second layer by supplying a hydrogen nitride-based gas to the substrate to nitride the first layer; and (c) modifying a part of the NH termination to an N termination, and maintaining another part of the NH termination as it is without modifying the another part to the N termination by plasma-exciting and supplying a nitrogen gas to the substrate, wherein in (c), an N termination ratio in an upper portion of the concave portion of the pattern is made higher than an N termination ratio in a lower portion of the concave portion of the pattern.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: November 26, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Katsuyoshi Harada, Satoshi Shimamoto
  • Patent number: 10483463
    Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Giorgio Servalli, Carmela Cupeta, Fabio Pellizzer
  • Patent number: 10483167
    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. A hard mask and a mask layer are formed on a first region and a second region of the substrate. The substrate is recessed using the hard mask and the mask layer to form a fin structure in the first region and a raised structure in the second region. First isolation structures and second isolation structures are formed on lower portions of opposite sidewalls of the fin structure and opposite sidewalls of the raised structure. A first gate structure is formed on a portion of the fin structure, and a second gate structure is formed on a portion of the raised structure. A first source and a first drain are formed on opposite sides of the first gate structure, and a second source and a second drain are formed on opposite sides of the second gate structure.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Barn Chen, Ting-Huang Kuo, Shiu-Ko Jangjian, Chi-Cherng Jeng, Kuang-Yao Lo
  • Patent number: 10479675
    Abstract: A semiconductor device production method includes performing trench etching to form a trench in a thickness direction of a semiconductor layer so that both of a first pattern portion and a second pattern portion whose side walls face each other across the trench are formed. In the trench etching, the semiconductor layer is etched and removed while a protective film is formed on a surface of the semiconductor layer, and the trench etching is performed so that the first pattern portion and the second pattern portion are configured to have a same potential or a same temperature during the trench etching.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: November 19, 2019
    Assignee: DENSO CORPORATION
    Inventors: Akira Ogawa, Yoshitaka Noda, Tetsuo Yoshioka, Yuhei Shimizu
  • Patent number: 10483162
    Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a dielectric layer with an opening on the substrate; forming a first barrier layer on sidewall and bottom surfaces of the opening, the first barrier layer being doped by manganese; and forming a metal interconnect on the first barrier layer, the metal interconnect being located within the opening.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: November 19, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Hao Deng
  • Patent number: 10476037
    Abstract: Disclosed is a flexible display apparatus. The flexible display apparatus includes a display part, a first adhesive film, an optical film, a second adhesive film, and a window film sequentially stacked, and the second adhesive film has a water-vapor permeability of about 200 g/m2·24 hr or less, and the first adhesive film has a lower restoration force than the second adhesive film, as calculated by the Equation B set forth herein.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: November 12, 2019
    Assignees: Samsung SDI Co., Ltd., Samsung Electronics Co., Ltd.
    Inventors: Sung Hyun Mun, Byeong Do Kwak, Ji Won Kang, Il Jin Kim, Ji Ho Kim, Hyung Rang Moon, Seon Hee Shin, Gwang Hwan Lee, Jin Young Lee, Ik Hwan Cho, Jae Hyun Han, In Chul Hwang
  • Patent number: 10476043
    Abstract: A display including a back plate, a plurality of light emitting devices and a plurality of compensating light emitting devices is provided. The back plate has a plurality of pixels and at least one compensated region. The compensated region includes some of the pixels. The light emitting devices are arranged in all the pixels on the back plate. The compensated light emitting devices are disposed on the back plate and located in each pixel in the compensated region respectively. At least one of the pixels in the compensated region is dead pixel. Besides, a repair method of the display is also provided.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: November 12, 2019
    Assignee: PlayNitride Inc.
    Inventors: Yu-Hung Lai, Yun-Li Li, Tzu-Yang Lin
  • Patent number: 10468402
    Abstract: A method for forming a trench diode for a power semiconductor device includes forming a first trench having a first opening and a second trench having a second opening in a substrate material, the second opening of the second trench being wider than the first opening of the first trench. An insulating layer is formed over surfaces of the first and second trenches. A first semiconductor material is provided within the first and second trenches, the first semiconductor material filling the first trench at least until the first opening is entirely plugged and partially filling the second trench so that a portion of the second opening remains open, the first semiconductor material having a first conductivity type. A second semiconductor material is provided within the second trench and over the first semiconductor material, the second semiconductor material having a second conductivity type that is different from the first conductivity type.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: November 5, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jongho Park, Sangsu Woo, SangYong Lee, SeWoon Kim
  • Patent number: 10461015
    Abstract: Single-layer CNT composites and multilayered or multitiered structures formed therefrom, by stacking of vertically aligned carbon nanotube (CNT) arrays, and methods of making and using thereof are described herein. Such multilayered or multitiered structures can be used as thermal interface materials (TIMs) for a variety of applications, such as burn-in testing.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: October 29, 2019
    Assignee: CARBICE CORPORATION
    Inventors: Baratunde Cola, Craig Green, Leonardo Prinzi
  • Patent number: 10439098
    Abstract: To provide a method for producing a Group III nitride semiconductor light-emitting device, which allows the formation of a high-temperature AlN buffer layer on an uneven substrate. This production method comprises forming an Al layer or Al droplets on the uneven shape of the uneven substrate, forming an AlN buffer layer while nitriding the Al layer; and forming a Group III nitride semiconductor layer on the AlN buffer layer. In the forming an Al layer, the internal pressure of a furnace is 1 kPa to 19 kPa, the temperature of the uneven substrate is 900° C. to 1,500° C., and an organic metal gas containing Al is supplied at a flow rate of 1.5×10?4 mol/min or more.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: October 8, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Koji Okuno
  • Patent number: 10436946
    Abstract: Transfer films, articles made therewith, and methods of making and using transfer films that include antireflective structures are disclosed.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: October 8, 2019
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Michael Benton Free, Justin P. Meyer, Olester Benson, Jr., Terry O. Collier, Mieczyslaw H. Mazurek, Martin B. Wolk, Moses M. David
  • Patent number: 10438815
    Abstract: In a semiconductor device including an oxide semiconductor, a change in electrical characteristics is inhibited and reliability is improved. The semiconductor device is manufactured by a method including first to fourth steps. The first step includes a step of forming an oxide semiconductor film, the second step includes a step of forming an oxide insulating film over the oxide semiconductor film, the third step includes a step of forming a protective film over the oxide insulating film, and the fourth step includes a step of adding oxygen to the oxide insulating film through the protective film. In the first step, the oxide semiconductor film is formed under a condition in which an oxygen vacancy is formed. The oxygen from the oxide insulating film fills the oxygen vacancy after the fourth step.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: October 8, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Daisuke Kurosaki, Yukinori Shima, Takuya Handa
  • Patent number: 10431715
    Abstract: A device and a method for producing a device are disclosed. In an embodiment the device includes a first component; a second component; and a connecting element arranged between the first component and the second component, wherein the connecting element comprises at least a first phase and a second phase, wherein the first phase comprises a first metal having a first concentration, a second metal having a second concentration and a third metal having a third concentration, wherein the second phase comprises the first metal having a fourth concentration, the second metal and the third metal, wherein the first metal, the second metal and the third metal are different from one another and are suitable for reacting at a processing temperature of less than 200° C., and wherein the following applies: c11?c25 and c11?c13?c12.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: October 1, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Barbara Behr, Andreas Weimar, Mathias Wendt, Marcus Zenger
  • Patent number: 10431722
    Abstract: A light emitting element includes: a semiconductor stack structure that includes a light emitting part, and a light receiving part that receives light propagating in a lateral direction through a semiconductor layer from the light emitting part, wherein the light emitting part and the light receiving part share a quantum layer; and a light reflection layer that covers ? or more of a lateral surface of the quantum layer in the light receiving part.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: October 1, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Junichiro Hayakawa, Akemi Murakami, Takashi Kondo, Naoki Jogan, Jun Sakurai
  • Patent number: 10431633
    Abstract: A method for producing a component is provided, where the component comprises a substrate, which emits at least one electromagnetic radiation in a first wavelength range and an electromagnetic radiation in a second wavelength range within one surface area. Electrodes can be formed within the surface area of the substrate; a first layer stack can be deposited, comprising at least one layer, which causes the emission of the electromagnetic radiation in the first wavelength range, and a cover layer, acting as the first counterelectrode, on the entire surface area; the first layer stack can be removed from a first partial surface area, which comprises at least one electrode; a second layer stack can be deposited, comprising at least one layer, which causes the emission of the electromagnetic radiation in the second wavelength range, and a second cover layer, acting as the counterelectrode, on the entire surface area.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: October 1, 2019
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Volker Kirchhoff, Uwe Vogel, Elisabeth Bodenstein, Beatrice Beyer, Stefan Saager, Karsten Fehse, Bernd Richter, Philipp Wartenberg, Mario Metzner, Christoph Metzner, Matthias Schober, Susan Mühl
  • Patent number: 10424536
    Abstract: Electronic component having a first lead frame consisting of an electrically conductive material. The first lead frame carries a first semiconductor component. In the plane of the lead frame a shunt element is arranged, wherein the shunt element comprises a resistor body arranged between a first terminal contact and a second terminal contact. An electrically conducting connection extends from a terminal of the first semiconductor component through the first lead frame to the first terminal contact of the shunt element. A current measurement with good accuracy is facilitated.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: September 24, 2019
    Assignee: SCHWEIZER ELECTRONIC AG
    Inventors: Thomas Gottwald, Christian Rössle
  • Patent number: 10403843
    Abstract: Light-emitting elements in which an increase of driving voltage can be suppressed are provided. Light-emitting devices whose power consumption is reduced by including such light-emitting elements are also provided. In a light-emitting element having an EL layer between an anode and a cathode, a first layer in which carriers can be produced is formed between the cathode and the EL layer and in contact with the cathode, a second layer which transfers electrons produced in the first layer is formed in contact with the first layer, and a third layer which injects the electrons received from the second layer into the EL layer is formed in contact with the second layer.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: September 3, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromi Nowatari, Satoshi Seo, Nobuharu Ohsawa, Tetsuo Tsutsui
  • Patent number: 10403820
    Abstract: A method for continuously preparing organic light emitting diode (OLED) by using thermal transfer film is revealed. At least two thermal transfer layers are transferred onto a substrate in turn by thermal transfer printing for overcoming shortcomings of the conventional vacuum evaporation including complicated processes and low material efficiency. Only less than 50% material reaches the substrate after the vacuum evaporation.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: September 3, 2019
    Assignee: Chien-Hwa Coating Technology, Inc.
    Inventor: Hung-Hsin Shih