Patents Examined by Andres Munoz
  • Patent number: 11830804
    Abstract: Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 28, 2023
    Assignee: Invensas LLC
    Inventors: Belgacem Haba, Stephen Morein, Ilyas Mohammed, Rajesh Katkar, Javier A. Delacruz
  • Patent number: 11810986
    Abstract: A method for integrating a surface-electrode ion trap and a silicon optoelectronic device, and an integrated structure. A silicon structure and a grating are formed on a wafer. A first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer are sequentially deposited above the wafer. An epitaxy opening is provided in the first dielectric layer to form single-photon avalanche detectors. First contacts vias connecting the detectors, and through silicon vias reaching a back surface of the wafer, are provided in the second dielectric layer and the third dielectric layer, respectively. Electrodes, the second contact vias and the third contact vias are provided in the fourth dielectric layer. The first contact vias are connected to a first electrode via the second contact vias, and the through silicon vias are connected to the first electrode and a second electrode via the third contact vias.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: November 7, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yan Yang, Zhihua Li, Wenwu Wang
  • Patent number: 11804525
    Abstract: An epitaxial structure includes a semiconductor substrate, a dislocation blocking layer; and one or more active layers.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: October 31, 2023
    Inventors: John Bowers, Justin Norman, Kunal Mukherjee, Jennifer Selvidge, Eamonn Hughes
  • Patent number: 11804518
    Abstract: A semiconductor device includes a capacitor including a lower electrode an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes ABO3 where ‘A’ is a first metal element and ‘B’ is a second metal element having a work function greater than that of the first metal element. The dielectric layer includes CDO3 where ‘C’ is a third metal element and ‘D’ is a fourth metal element. The lower electrode includes a first layer and a second layer which are alternately and repeatedly stacked. The first layer includes the first metal element and oxygen. The second layer includes the second metal element and oxygen. The dielectric layer is in contact with the lower electrode at a first contact surface the first contact surface corresponding to the second layer.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: October 31, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jungmin Park, Haeryong Kim, Young-geun Park
  • Patent number: 11798808
    Abstract: A method of Atomic Precision Advanced Manufacturing (APAM) is provided, in which a substrate is doped from a dopant precursor gas. The method involves covering a surface of the substrate with a hard mask, selectively removing material from the hard mask such that selected areas of the substrate surface are laid bare, exposing the laid-bare areas to the dopant precursor gas, and heating the substrate so as to incorporate dopant from the dopant precursor gas into the substrate surface.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: October 24, 2023
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Shashank Misra, Daniel Robert Ward, DeAnna Marie Campbell, Tzu-Ming Lu, Scott William Schmucker, Evan Michael Anderson, Andrew Jay Leenheer, Jeffrey Andrew Ivie
  • Patent number: 11785791
    Abstract: Devices, structures, materials and methods for carbon enabled vertical light emitting transistors (VLETs) and light emitting displays (LEDs) are provided. In particular, architectures for vertical polymer light emitting transistors (VPLETs) for active matrix organic light emitting displays (AMOLEDs) and AMOLEDs incorporating such VPLETs are described. Carbon electrodes (such as from graphene) alone or in combination with conjugated light emitting polymers (LEPs) and dielectric materials are utilized in forming organic light emitting transistors (OLETs). Combinations of thin films of ionic gels, LEDs, carbon electrodes and relevant substrates and gates are utilized to construct LETs, including heterojunction VOLETs.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: October 10, 2023
    Assignee: Atom H2O, LLC
    Inventor: Huaping Li
  • Patent number: 11764066
    Abstract: A peeling method for peeling off a substrate provided over a front surface of a support plate through a peel layer from the support plate after dividing the substrate into a plurality of small pieces, the peeling method comprising: a first holding step of holding the support plate by a first holding unit; a dividing step of causing a cutting blade to cut into the substrate, or applying a laser beam of such a wavelength as to be absorbed in the substrate to the substrate, along division lines set on the substrate, to divide the substrate into the plurality of small pieces; a start point region forming step of blowing a fluid to the peel layer exposed at an end portion of a small piece among the plurality of small pieces, to form a start point region which will serve as a start point when peeling off the small piece from the support plate; a second holding step of holding the small piece by a second holding unit; and a peeling step of relatively moving the first holding unit and the second holding unit in direc
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: September 19, 2023
    Inventor: Katsuhiko Suzuki
  • Patent number: 11764318
    Abstract: A Semiconductor device includes an insulating layer, an optical waveguide, a first dummy semiconductor film, a second semiconductor film and a third semiconductor film. The optical waveguide is formed on the insulating layer. The first dummy semiconductor film is formed on the insulating layer and is spaced apart from the optical waveguide. The first dummy semiconductor film is formed on the first semiconductor film. The second semiconductor film is integrally formed with the optical waveguide as a single member on the insulating layer. The third semiconductor film is formed on the second semiconductor film. A material of the first dummy semiconductor film is different from a material of the optical waveguide. In plan view, a distance between the optical waveguide and the first dummy semiconductor film in a first direction perpendicular to an extending direction of the optical waveguide is greater than a thickness of the insulating layer.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: September 19, 2023
    Inventors: Shotaro Kudo, Shinichi Watanuki, Takashi Ogura
  • Patent number: 11735679
    Abstract: A silicon based photodetector and method of manufacturing the same are provided. The photodetector comprising: a silicon substrate; a buried oxide layer, above the silicon substrate; and a waveguide, above the buried oxide layer. The waveguide includes a silicon, Si, containing region and a germanium tin, GeSn, containing region, both located between a first doped region and a second doped region of the waveguide, thereby forming a PIN diode. The first doped region and the second doped region are respectively connected to first and second electrodes, such that the waveguide is operable as a photodetector.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: August 22, 2023
    Assignee: Rockley Photonics Limited
    Inventors: Yi Zhang, Hooman Abediasl, Aaron John Zilkie
  • Patent number: 11735509
    Abstract: Provided are a power semiconductor device using a lead frame, in which deformation and bending of terminals is suppressed, insulation is secured between terminals, and mounting onto a control board is facilitated, and a manufacturing method thereof. A package in which a semiconductor element mounted on a lead frame is sealed, terminals being bent and exposed from side surfaces of the package, and, a terminal bending portion being a portion bent in each of the terminals, a width thereof being larger than a width of a tip of the terminal, and being equal to or smaller than the width of a contact portion of the terminal in contact with the package are provided; therefore, deformation and bending of the terminals is suppressed, a necessary insulation is secured between the adjacent terminals, and mounting onto a control board is facilitated.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: August 22, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Keitaro Ichikawa, Taketoshi Shikano, Yuji Shikasho, Fumihito Kawahara
  • Patent number: 11728434
    Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: August 15, 2023
    Inventors: Seok Hoon Kim, Dong Myoung Kim, Dong Suk Shin, Seung Hun Lee, Cho Eun Lee, Hyun Jung Lee, Sung Uk Jang, Edward Nam Kyu Cho, Min-Hee Choi
  • Patent number: 11715707
    Abstract: Described examples include an apparatus including a package substrate having a die attach pad and a first semiconductor die on the die attach pad, the first semiconductor die including a transmitter. The apparatus also includes an assembly having a first plate coupled to the transmitter, a second plate separated from the first plate by a dielectric and a second semiconductor die on the die attach pad, the second semiconductor die including a receiver coupled to the second plate.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: August 1, 2023
    Inventors: Sreeram SubramanyamNasum, Vijaylaxmi Khanolkar, Tarunvir Singh
  • Patent number: 11676932
    Abstract: Semiconductor devices having interconnect structures with narrowed portions configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include an end portion away from the semiconductor die, the end portion having a first cross-sectional area. The pillar structure can further include a narrowed portion between the end portion and the semiconductor die, the narrowed portion having a second cross-sectional area less than the first-cross-sectional area of the end portion. A bond material can be coupled to the end portion of the pillar structure.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hyunsuk Chun, Thiagarajan Raman
  • Patent number: 11665924
    Abstract: A display panel and a display device are provided. The display panel includes a substrate; a plurality of sub-pixels, each of which includes a light-emitting elements; a thin-film encapsulation layer located at a side of the light-emitting element facing away from the substrate and including a plurality of inorganic encapsulation layers and a plurality of organic encapsulation layers that are alternately stacked, at least one of the plurality of organic encapsulation layers being an organic color conversion layer configured to convert a color of light emitted by the light-emitting element; and a color filter layer located at a side of the thin film encapsulation layer facing away from the substrate.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: May 30, 2023
    Assignee: WuHan TianMa Micro-electronics Co., Ltd
    Inventor: Sitao Huo
  • Patent number: 11659722
    Abstract: Embodiments herein describe techniques for a semiconductor device including a semiconductor substrate, a first device of a first wafer, and a second device at back end of a second wafer, where the first device is bonded with the second device. A first metal electrode of the first device within a first dielectric layer is coupled to an n-type oxide TFT having a channel layer that includes an oxide semiconductor material. A second metal electrode of the second device within a second dielectric layer is coupled to p-type organic TFT having a channel layer that includes an organic material. The first dielectric layer is bonded to the second dielectric layer, and the first metal electrode is bonded to the second metal electrode. The n-type oxide TFT and the p-type organic TFT form a symmetrical pair of transistors of a CMOS circuit. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Prashant Majhi, Ravi Pillarisetty, Elijah Karpov, Brian Doyle, Anup Pancholi, Abhishek Sharma
  • Patent number: 11646252
    Abstract: A semiconductor device includes a semiconductor chip, a connection element configured to mechanically and electrically couple the semiconductor device to a circuit board, wherein the connection element is electrically coupled to the semiconductor chip and arranged in a mounting plane of the semiconductor device, and the semiconductor chip is mounted on the connection element. The semiconductor device further includes an extension element mechanically coupled to the connection element and extending in a direction out of the mounting plane, wherein the extension element is configured for air cooling.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: May 9, 2023
    Assignee: Infineon Technologies AG
    Inventor: Tomasz Naeve
  • Patent number: 11631641
    Abstract: Provided is a semiconductor device including: a circuit board; a wiring pattern; a first semiconductor chip and a second semiconductor chip; a first lead frame; and a second lead frame; wherein the first lead frame and the second lead frame each comprises: a chip joining portion provided above at least a part of the semiconductor chip; a wiring joining portion provided above at least a part of the wiring pattern; and a bridging portion for connecting the chip joining portion and the wiring joining portion; and in the first direction, a space between the bridging portion of the first lead frame and the bridging portion of the second lead frame is smaller than a space between the chip joining portion of the first lead frame and the chip joining portion of the second lead frame.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: April 18, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tomoya Nakayama, Akihiro Osawa
  • Patent number: 11611020
    Abstract: A light emitting element including a housing having a cavity and an inner wall, a light emitting part disposed in the cavity to emit light having a peak wavelength in a blue wavelength band and including first and second light emitting chips spaced apart from each other, a lead portion to supply external electric power, and a wavelength converter including a first phosphor layer including a first phosphor to emit light having a peak wavelength in a green wavelength band, and a second phosphor layer including a second phosphor to emit light having a peak wavelength in a red wavelength band, in which the second phosphor includes at least one of a nitride-based red phosphor and a fluoride-based red phosphor represented by A2MF6:Mn4+, A is one of Li, Na, K, Ba, Rb, Cs, Mg, Ca, Se, and Zn, and M is one of Ti, Si, Zr, Sn, and Ge.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: March 21, 2023
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Ho Jun Byun, Bo Yong Han
  • Patent number: 11594595
    Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: February 28, 2023
    Inventors: Jong-Min Lee, Hyongsoo Kim, Jongryul Jun
  • Patent number: 11581452
    Abstract: A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. Precursor stacks having at least one precursor metal are situated over at least one portion of the patterned group III-V device. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over each precursor stack. A filler metal is situated in each contact hole and over each precursor stack. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate. Additional contact holes in the blanket dielectric layer can be situated over the group IV devices and filled with the filler metals.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: February 14, 2023
    Assignee: Newport Fab, LLC
    Inventors: Edward Preisler, Zhirong Tang