Abstract: A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a capped gate structure is formable and from source and drain (S/D) contact spaces and growing III-V semiconductor materials in the S/D contact spaces.

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.

Abstract: A method of fabricating a high-crystalline-quality and high-uniformity AlN layer within a high electron mobility transistor (HEMT) device with a metalorganic chemical vapor deposition (MOCVD) technique, includes: raising a temperature of a substrate to an ultra-high growth temperature; and supplying an Al source and an N source in pulses over the substrate under the ultra-high growth temperature, wherein the ultra-high growth temperature is at least 1300° C. At least for a first predetermined period of time in each cycle of the pulses, the Al source is switched on when the N source is switched off.

Abstract: A light-emitting device includes a carrier, a light-emitting unit disposed on the carrier, a reflective element arranged on the light-emitting unit, and an optical element arranged on the carrier and surrounding the light-emitting unit.

Abstract: A vertical memory device includes first, second and third impurity regions sequentially stacked in a first direction substantially perpendicular to an upper surface of a substrate, a gate electrode structure including gate electrodes spaced apart from each other in the first direction on the third impurity region, a channel extending through the gate electrode structure, the second and third impurity regions, and an upper portion of the first impurity region on the substrate in the first direction, and a charge storage structure covering a portion of an outer sidewall and a lower surface of the channel. The channel directly contacts a sidewall of the second impurity region.

Abstract: A self-align metal contact for a phase control memory (PCM) element is provided that mitigates unwanted residual tantalum nitride (TaN) particles that would otherwise remain after patterning a TaN surface using an RIE process.

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

Abstract: A device includes first and second transistors and first and second isolation structures. The first transistor includes an active region including a first channel region, a first source and a first drain in the active region and respectively on opposite sides of the first channel region, and a first gate structure over the first channel region. The first isolation structure surrounds the active region of the first transistor. The second transistor includes a second source and a second drain, a fin structure includes a second channel region between the second source and the second drain, and a second gate structure over the second channel region. The second isolation structure surrounds a bottom portion of the fin structure of the second transistor. The top of the first isolation structure is higher than a top of the second isolation structure.

Abstract: An organic light emitting diode display panel includes a thin film transistor array layer disposed on a flexible substrate, and including thin film transistors, a reflective anode, and a pixel defining layer. The pixel defining layer has a patterned structure defining non-light emitting regions and light emitting regions, each being between the non-light emitting regions; a black matrix layer disposed on the non-light emitting regions; a light emitting module disposed on a surface of the black matrix layer and the pixel defining layer, and including a plurality of pixel units. Each pixel unit includes a red subpixel, a green subpixel, and a blue subpixel respectively correspondingly disposed in one light emitting region and disposed on the reflective anode; a filter film layer including a red filter, a green filter, and a blue filter respectively correspondingly disposed on one red subpixel, one green subpixel and one blue subpixel.

Abstract: Techniques are disclosed for producing integrated circuit structures that include one or more geometrically manipulated polarization layers. The disclosed structures can be formed, for instance, using spacer erosion methods in which more than one type of spacer material is deposited on a polarization layer, and the spacer materials and underlying regions of the polarization layer may then be selectively etched in sequence to provide a desired profile shape to the polarization layer. Geometrically manipulated polarization layers as disclosed herein may be formed to be thinner in regions closer to the gate than in other regions, in some embodiments. The disclosed structures may eliminate the need for a field plate and may also be configured with polarization layers that are shorter in lateral length than polarization layers of uniform thickness without sacrificing performance capability. Additionally, the disclosed techniques may provide increased voltage breakdown without sacrificing Ron.

Abstract: A cross-point array device includes a substrate, a first conductive line disposed over the substrate and extending in a first direction, a plurality of pillar structures disposed on the first conductive line, each of the pillar structure comprising a memory electrode, a resistive memory layer disposed along surfaces of the pillar structures, a threshold switching layer disposed on the resistive memory layer, and a second conductive line electrically connected to the threshold switching layer and extending a second direction that is not parallel to the first conductive line.

Abstract: A semiconductor wafer processing method includes a step of forming a laser processed groove on the front side of a semiconductor wafer along each division line, a step of forming a mask layer on a protective layer except in an area above a metal electrode formed in each device on the front side of the wafer, a first etching step of etching the protective layer by using the mask layer to expose each metal electrode, a second etching step of etching the inner surface of each laser processed groove by using the mask layer used in the first etching step, thereby expanding each laser processed groove, and a dividing step of dividing the wafer along each laser processed groove expanded in the second etching step.

Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

Abstract: A transistor may include a semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region. The channel region may have a source interface and a drain interface, and may be bounded by edges extending from the source interface to the drain interface on two boundaries between a field-sensitive semiconductor material and an isolation material. The transistor may further include an insulator layer on the channel region. The transistor may further include a gate on the insulator layer. The gate may have extensions beyond edges of the channel region. The extensions may substantially exceed a minimum specified value.

Abstract: A semiconductor device including one or more semiconductor dice, a lead frame including an array of signal-carrying leads electrically coupled with the semiconductor die, and a power supply connection for the at least one semiconductor die arranged centrally thereof.

Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

Abstract: A method for manufacturing a silicon epitaxial wafer includes: preparing a test silicon wafer in advance, forming the multilayer film on a surface of the test silicon wafer, and measuring a warp direction and a warp amount (Warp) W of the silicon wafer having the multilayer film formed thereon; and selecting a silicon wafer as a device formation substrate and conditions for forming an epitaxial layer which is formed on the silicon wafer as the device formation substrate in such a manner that a warp which cancels out the measured warp amount W is formed in a direction opposite to the measured warp direction, and forming the epitaxial layer on a surface of the selected silicon wafer as the device formation substrate where the multilayer film is formed under the selected conditions for forming the epitaxial layer.

Abstract: A method to reduce the number and type of processing steps to achieve conductive lines in the planes of a substrate concurrently interconnecting conductor through the substrate, by forming structures in the planes of a substrate. These structures may include interconnect lines, bond pads, and other structures, and improve the performance of subsequent unique processing while simultaneously reducing the manufacturing complexity to reduce time and cost. These structures are formed by selective etching using chemical mechanical polishing, and then completed using a single fill step with a conductive material.

Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.