Patents Examined by Andres Munoz
  • Patent number: 11328958
    Abstract: A device includes first and second transistors and first and second isolation structures. The first transistor includes a raised structure, a first gate structure over the raised structure, and a first source/drain structure over the raised structure and adjacent the first gate structure. The first isolation structure surrounds the raised structure and the first source/drain structure of the first transistor. A bottommost surface of the first source/drain structure is spaced apart from a topmost surface of the first isolation structure. The second transistor includes a fin structure, a second gate structure over the raised structure, and a second source/drain structure over the fin structure. The second isolation structure surrounds a bottom of the fin structure of the second transistor. A bottommost surface of the second source/drain structure is in contact with a topmost surface of the second isolation structure.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Barn Chen, Ting-Huang Kuo, Shiu-Ko Jangjian, Chi-Cherng Jeng, Kuang-Yao Lo
  • Patent number: 11322669
    Abstract: A nano-structure layer is disclosed. The nano-structure layer includes an array of nano-structure material configured to receive a first light beam at a first angle of incidence and to emit the first light beam at a second angle greater than the first angle, the nano-structure material each having a largest dimension of less than 1000 nm.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 3, 2022
    Assignee: Lumileds LLC
    Inventors: Antonio Lopez-Julia, Venkata Ananth Tamma
  • Patent number: 11316064
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one fin including substrate material, the at least one fin including sidewalls and a top surface; a trench on opposing sides of the at least one fin; a first semiconductor material lining the sidewalls and the top surface of the at least one fin, and a bottom surface of the trench; a photosensitive semiconductor material on the first semiconductor material and at least partially filling the trench; and a third semiconductor material on the photosensitive semiconductor material.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 26, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Siva P. Adusumilli, John J. Ellis-Monaghan, Mark D. Levy, Vibhor Jain, Andre Sturm
  • Patent number: 11302603
    Abstract: Single-layer CNT composites and multilayered or multitiered structures formed therefrom, by stacking of vertically aligned carbon nanotube (CNT) arrays, and methods of making and using thereof are described herein. Such multilayered or multitiered structures can be used as thermal interface materials (TIMs) for a variety of applications, such as burn-in testing.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: April 12, 2022
    Assignee: CARBICE CORPORATION
    Inventors: Baratunde Cola, Craig Green, Leonardo Prinzi
  • Patent number: 11302669
    Abstract: Methods, systems and devices are disclosed for performing a semiconductor processing operation. In some embodiments this includes configuring a wire bonding machine to perform customized movements with a capillary tool of the wire bonding machine, etching bulk contaminants over one or more locations of a semiconductor device with the capillary tool, and applying plasma to the semiconductor device to remove residual contaminants.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: April 12, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventors: Aldrin Quinones Garing, Miguel Camargo Soto
  • Patent number: 11296246
    Abstract: The present disclosure relates to a photosensitive component, a detection substrate and a method for manufacturing the detection substrate. The photosensitive component includes: a first electrode layer, a photoelectric conversion layer, a second electrode layer, an insulating layer and a reflective layer. The photoelectric conversion layer is located on the first electrode layer. The second electrode layer is located on a surface of the photoelectric conversion layer away from the first electrode layer. The insulating layer covers side surfaces of the photoelectric conversion layer and at least a part of a surface of the second electrode layer away from the photoelectric conversion layer, and the insulating layer includes a transparent material. The reflective layer covers the insulating layer, and the reflective layer is configured to reflect at least a part of light entering the insulating layer to the side surfaces of the photoelectric conversion layer.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: April 5, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Rui Huang
  • Patent number: 11289564
    Abstract: A double-sided display panel and a method for manufacturing the same are provided. The double-sided display panel includes: a first substrate; a second substrate opposite to first substrate; a first display unit between the first substrate and the second substrate, the first display unit including a first luminescent layer and a first reflective layer which is closer to the second substrate than the first luminescent layer, wherein at least a part of light emitted from the first luminescent layer is reflected by the first reflective layer and emitted out through the first substrate; and a second display unit between the first substrate and second substrate, including a second luminescent layer, wherein light emitted from the second luminescent layer is emitted out through the second substrate. The first display unit includes a transparent electrode and a conductive contact layer which electrically connects the transparent electrode with the first reflective layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: March 29, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xuehuan Feng, Yongqian Li
  • Patent number: 11289649
    Abstract: Structures for a non-volatile memory element and methods of forming a structure for a non-volatile memory element. A switching layer is positioned over a first electrode, and a dielectric layer is positioned over the switching layer. The dielectric layer includes an opening extending to the switching layer. A second electrode includes a portion in the opening in the dielectric layer. The portion of the second electrode is in contact with a first portion of the switching layer. The switching layer further includes a second portion positioned between the dielectric layer and the first electrode.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: March 29, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Lup San Leong, Curtis Chun-I Hsieh, Juan Boon Tan, Eng Huat Toh, Kin Wai Tang
  • Patent number: 11289378
    Abstract: A method for forming semiconductor devices from a semiconductor wafer includes cutting a first surface of a semiconductor wafer to form a first region that extends partially through the semiconductor wafer and the first region has a bottom portion. The method further includes directing a beam of laser light to the semiconductor wafer such that the beam of laser light is focused within the semiconductor wafer between the first surface and the second surface thereof and the beam of laser light further cuts the semiconductor wafer by material ablation to form a second region aligned with the first region. A resulting semiconductor device is disclosed as well.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 29, 2022
    Assignee: WOLFSPEED, INC.
    Inventors: Kevin Schneider, Alexander Komposch
  • Patent number: 11276682
    Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: March 15, 2022
    Assignee: Newport Fab, LLC
    Inventors: Mantavya Sinha, Edward Preisler, David J. Howard
  • Patent number: 11276770
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate controlled transistors and methods of manufacture. The structure includes: an emitter region; a collector region; base regions on opposing sides of the emitter region and the collector region; and a gate structure composed of a body region and leg regions, the body region being located between the base regions on opposing sides of the emitter region and the collector region, and the leg regions isolating the base regions from both the emitter region and the collector region.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: March 15, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Mankyu Yang, Jagar Singh, Alexander Martin, John J. Ellis-Monaghan
  • Patent number: 11271134
    Abstract: A method for manufacturing an optical sensor is provided. The method comprises providing an optical sensor arrangement which comprises at least two optical sensor elements on a carrier, where the optical sensor arrangement comprises a light entrance surface at the side of the optical sensor elements facing away from the carrier. The method further comprises forming a trench between two optical sensor elements in a vertical direction which is perpendicular to the main plane of extension of the carrier, where the trench extends from the light entrance surface of the sensor arrangement at least to the carrier. Moreover, the method comprises coating the trench with an opaque material, forming electrical contacts for the at least two optical sensor elements on a back side of the carrier facing away from the optical sensor elements, and forming at least one optical sensor by dicing the optical sensor arrangement along the trench.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: March 8, 2022
    Assignee: AMS AG
    Inventors: Gregor Toschkoff, Thomas Bodner, Franz Schrank, Miklos Labodi, Joerg Siegert, Martin Schrems
  • Patent number: 11270941
    Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Thomas Wagner, Andreas Wolter, Bernd Waidhas
  • Patent number: 11264336
    Abstract: In a described example, an apparatus includes a packaged device carrier having a board side surface and an opposing surface, the packaged device carrier having conductive leads having a first thickness spaced from one another; the conductive leads having a head portion attached to a dielectric portion, a middle portion extending from the head portion and extending away from the board side surface of the packaged device carrier at an angle to the opposing surface, and each lead having an end extending from the middle portion with a foot portion configured for mounting to a substrate.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: March 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K. Koduri
  • Patent number: 11264498
    Abstract: A semiconductor device includes a semiconductor substrate, a first source region, a first drain region, a first gate, a second source region, a second drain region, a second gate, and a first dielectric layer. The first source region and the first drain region are disposed within the semiconductor substrate. The first gate is disposed over the semiconductor substrate in between the first source region and the first drain region. The second source region and the second drain region are disposed within the semiconductor substrate. The second gate is disposed over the semiconductor substrate in between the second source region and the second drain region. The first dielectric layer is located in between the first gate and the semiconductor substrate, and in between the second gate and the semiconductor substrate, wherein the first dielectric layer extends from a position below the first gate to a position below the second gate.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gerben Doornbos, Blandine Duriez, Georgios Vellianitis, Marcus Johannes Henricus Van Dal, Mauricio Manfrini
  • Patent number: 11258011
    Abstract: An RRAM structure and its manufacturing method are provided. The RRAM structure includes a bottom electrode layer, a resistance switching layer, and an implantation control layer sequentially formed on a substrate. The resistance switching layer includes a conductive filament confined region and an outer region surrounding the conductive filament confined region. The RRAM structure includes a protective layer and a top electrode layer. The protective layer conformally covers the bottom electrode layer, the resistance switching layer, and the implantation control layer and has a first opening. The top electrode layer is located on the implantation control layer, and a portion of the top electrode layer is filled into the first opening. The position of the top electrode layer corresponds to that of the conductive filament confined region, and the top surface of the top electrode layer is higher than that of the protective layer.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: February 22, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Bo-Lun Wu, Po-Yen Hsu, Ting-Ying Shen, Meng-Hung Lin
  • Patent number: 11251244
    Abstract: A light-emitting device includes a substrate, a plurality of bumps over the substrate; and a plurality of light-emitting units separated by the bumps. Each of the light-emitting units includes a first electrode on the substrate, an organic layer on the first electrode, and a second electrode on the organic layer. The light-emitting units comprise a first light-emitting unit and a second light-emitting unit, and the first light-emitting unit further includes an intermediate layer between the organic layer and the second electrode. The organic layer of the first light-emitting unit includes a first material, the second electrodes of the first light-emitting unit and the second light-emitting unit include an electrode material, and the intermediate layer of the first light-emitting unit includes the first material and the electrode material.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: February 15, 2022
    Assignee: INT TECH CO., LTD.
    Inventors: Huei-Siou Chen, Li-Chen Wei
  • Patent number: 11239265
    Abstract: Example embodiments relate to single-photon avalanche diode detector (SPAD) arrays. One embodiment includes a SPAD array that includes a silicon substrate, a plurality of primary electrodes, and a plurality of secondary electrodes. Each of the primary electrodes includes a semiconductor material of a first doping type, extends in the silicon substrate in a first direction, and has a rotationally symmetric cross-section in a first plane perpendicular to the first direction. The plurality of secondary electrodes includes a semiconductor material of a second doping type and extends parallel to the primary electrodes in the silicon substrate. Further, the silicon substrate includes a doped upper field redistribution layer, a doped lower field redistribution layer, and a doped depletion layer arranged between the upper field redistribution layer and the lower field redistribution layer.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: February 1, 2022
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventor: Edward Van Sieleghem
  • Patent number: 11227768
    Abstract: The present disclosure is directed to a methodology for embedding a deterministic number of dopant atoms in a surface portion of a group IV semiconductor lattice. The methodology comprises the steps of: forming one or more lithographic sites on the surface portion; dosing, at a temperature below 100 K, the surface portion using a gas with molecules comprising the dopant atom and hydrogen atoms in a manner such that, a portion of the molecules bonds to the surface portion; and incorporating one or more dopant atoms in a respective lithographic site by transferring an amount of energy to the dopant atoms. The number of dopant atoms incorporated in a lithographic site is deterministic and related to the size of the lithographic site.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: January 18, 2022
    Assignee: NewSouth Innovations Pty Ltd
    Inventors: Michelle Simmons, Joris Keizer
  • Patent number: 11211254
    Abstract: A first dielectric layer made of a first dielectric material is deposited over a semiconductor substrate. A buffer layer is then deposited on an upper surface of the first dielectric layer. A trench is opened to extend through the buffer layer and the first dielectric layer. A second dielectric layer made of a second dielectric material is the deposited in a conformal manner on the buffer layer and filling the trench. Chemical mechanical polishing of the second dielectric layer is performed to remove overlying portions of the second dielectric layer with the buffer layer being used as a polish stop. After removing the buffer layer, the first dielectric layer and the second dielectric material filling the trench form a pre-metallization dielectric layer having a substantially planar upper surface.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: December 28, 2021
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Yuzhan Wang, Pradeep Basavanahalli Kumarswamy, Hong Kia Koh, Alberto Leotti, Patrice Ramonda