Abstract: A heat pipe comprising a wick, working fluid, a chamber housing the wick and working fluid, and a plurality of wraps of a graphite composite fiber, preferably THORNEL graphite fiber, number P-120 2K. For maximum strength, the wraps are in different directions. The heat pipe can be integrally incorporated and bound to a printed wiring board, thereby eliminating the need for additional inefficient thermal interfaces.

Abstract: A high electron mobility transistor (HEMT) includes a diffusion barrier (22) to prevent gate metal (20) diffusion into the substrate (12) during fabrication and a sacrificial platinum alloy layer (30) forms the Schottky barrier. A method of forming a HEMT includes forming a diffusion barrier of titanium nitride on a platinum layer and applying sufficient heat to cause the platinum layer to alloy with the gallium arsenide layer forming a platinum gallium and platinum arsenide alloy layer and Schottky barrier. Since all platinum is consumed, this method permits precise control of the thickness of the gate layer and eliminates diffusion of the platinum gate layer into the gallium arsenide layer during later processing steps.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

Abstract: Silicon MSM photodiodes sensitive to radiation in the visible to near infrared spectral range are produced by altering the absorption characteristics of crystalline Si by ion implantation. The implantation produces a defected region below the surface of the silicon with the highest concentration of defects at its base which acts to reduce the contribution of charge carriers formed below the defected layer. The charge carriers generated by the radiation in the upper regions of the defected layer are very quickly collected between biased Schottky barrier electrodes which form a metal-semiconductor-metal structure for the photodiode.

Abstract: A super-capacitor comprising a positive electrode, a negative electrode, both made of a p-doped electron conductive polymer, and an electrolyte. The electrolyte comprises an organic redox compound soluble in the electrolyte in an amount of at least 10.sup.-3 mole per liter. The redox potential of the redox compound lies in a non-capacitive region of the electron conductive polymer. The redox compound is reduced in a reversible manner at the negative electrode when the potential of the negative electrode is equal to or less than the redox potential of the redox compound, and the redox compound is oxidized in a reversible manner at the positive electrode when the potential of the positive electrode is equal to or more than the redox potential of the redox compound.

Abstract: A semiconductor device employs a lead frame including a die pad (24) and a plurality of leads (25) provided outside the die pad, and is manufactured by sealing the die pad and its periphery by a resin after the die pad is fitted with the semiconductor chip (11). The die pad (24) is formed separately from the main part of the lead frame provided with leads, and is rounded at an entire outermost edge thereof and includes a flat plate shape. This die pad can be either formed rounded with ceramic or resin, or formed in metal and given a rounded edge through honing.

Abstract: A programmable transistor includes impurity regions to reduce punch-through and soft-write phenomena. In order to provide a fast operation, the impurity regions are arranged with regard to one another so that parasitic capacitances at junctions of impurity regions of mutually opposite conductivity type are minimized. For these purposes, the transistor comprises a charge storage region over a channel region in a main semiconductor zone of a first conductivity type located between a source and a drain of a second conductivity type opposite to the first. A first impurity zone of the first conductivity type, substantially laterally contiguous with the drain, extends into the channel region and is more heavily doped than the main zone. The drain includes a heavily doped third impurity region and a lightly doped second impurity region that lies at least mainly between the third region and the zones.

Abstract: Only the areas of the CdTe/HgCdTe interface of a FPA detector circuit which is coupled by an epoxy to a silicon-based integrated circuit that require interdiffusing are heated to a sufficiently high temperature or have photons of light impinging thereon for a sufficient time to cause interdiffusion of the two layers by the travel of tellurium into the HgCdTe and the travel of mercury into the CdTe. The vast majority of the wafer is masked with an aluminum thin film to greatly reduce heat gain or photon transmission. An advantage of the process in accordance with the present invention is that only a very small fraction of the HgCdTe/epoxy/silicon-based integrated circuit wafer receives incoming energy during interdiffusion whereby problems caused by the differences in coefficient of thermal expansion between silicon and HgCdTe at the epoxy interface are minimized.

Abstract: A resin encapsulation type semiconductor device is provided with first leads electrically connected to the signal terminals of a semiconductor element and plate-like conductor elements electrically connected to the power source terminals of the semiconductor element. The first leads and the plate-like conductor elements are arranged in parallel with each other to form a two-layer structure. The number of the leads of the semiconductor element of the invented semiconductor device is reduced from that of the leads of the conventional semiconductor device. At least one through hole is formed in each of the plate-like conductor elements in a power source lead frame so as to make the flow distribution more uniform than in the plate-like conductor elements without the through holes.

Abstract: An integrated circuit is formed from a first layer of conductive material (30) which is separated from a second layer of conductive material (39) by a layer of dielectric material (36). The first layer of conductive material (30) is patterned to form a first plate (32, 59) of a capacitor (22, 50, 62, 72). An electrical interconnect (33, 63) is formed within the first plate (32, 59), respectively. A via (37) is formed in the layer of dielectric material (36). A second layer of conductive material (39) is patterned to form a second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72) and a planar spiral inductor (21, 51, 61, 71). The planar spiral inductor (21, 51, 61, 71) is surrounded by the second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72).

Abstract: An IC card includes: a circuit board on which functional components are mounted; and a frame covered with a thin plate, the circuit board being disposed in the frame, the inside of the frame being filled with a foamed resin. As a result of the above arrangement, an IC card having a strong resistance to various external forces is produced. Furthermore, because it is possible to incorporate a surface material with a design in an integrally molded device, thus it is also possible to produce an IC card device having an excellent appearance.

Abstract: A high-density semiconductor memory device has a self-aligning contact structure for electrical connection between lower and upper conductive layers, and an inter-insulating layer with a via for forming the contact structure. The contact structure has a contact pad including a first conductive layer electrically connected with the lower conductive layer within the via and formed on a predetermined portion of the inter-insulating layer around the groove, a planarizing material filling up the groove formed on the first conductive layer, and second conductive layers formed on the planarizing material and exposed first conductive layer.

Abstract: A semiconduct chip assembly includes a chip, terminals permanently electrically connected to the chip by flexible leads and a resilient element or elements for biasing the terminals away from the chip. The chip is permanently engaged with a substrate having contact pads so that the terminals are disposed between the chip and the substrate and the terminals engage the contact pads under the influence of the force applied by the resilient element. The terminals typically are provided on a flexible sheet-like dielectric interposer and the resilient element is disposed between the interposer and the chip. The assembly of the chip and the terminals can be tested prior to engagement with the substrate. Because engagement of this assembly with the substrate does not involve soldering or other complex bonding processes, it is reliable. The assembly can be extremely compact and may occupy an area only slightly larger than the area of the chip itself.

Abstract: A solid state, directly overwritable, electronic, non-volatile, high density, low cost, low energy, high speed, readily manufacturable, multibit single cell memory or control array based upon the novel switching characteristics provided by said unique class of semiconductor materials characterized by a large dynamic range of reversible Fermi level positions. The memory or control elements from which the array is fabricated exhibit orders of magnitude higher switching speeds at remarkably reduced energy levels. The novel memory elements of the instant invention are in turn characterized, inter alia, by numerous stable and non-volatile detectable configurations of local atomic and/or electrode order, which configurations can be selectively and repeatably accessed by electric input signals of yawing energy level.

Abstract: A radiation detector includes a photovoltaic diode mesa structure (16) having of a plurality of sub-mesa structures (16a, 16b). Each of said sub-mesa structures includes a first layer (14a) of semiconductor material having a first type of electrical conductivity and a second layer (14b) having a second type of electrical conductivity such that a p-n junction is formed between the first and the second layers. Metalization (24) is disposed within a trench (30a) that runs between the sub-mesas and includes a tab portion (24a) that extends upwardly over a sidewall of each of said sub-mesa structures so as to electrically contact the second layer contained within each. As a result, each of said sub-mesa structures are electrically connected in parallel.

Abstract: A packaging structure is disclosed for a semiconductor device, having a body configured to include at least one part provided with contact terminals and shaped to form a connector member for direct coupling to a standard connector member from an external circuit. A connector assembly is also disclosed which is fully sealed from moisture and comprises the packaging structure.

Abstract: Process for producing a transistor, particularly a heterojunction bipolar transistor, of the type comprising the known stages consisting in producing layers forming the collector, base and emitter, as well as collector, base and emitter ohmic contacts. The emitter producing stage consists in depositing, on the base layer, two superposed layers making up the emitter, the first of which is a thin layer made up of a first material having a large energy gap, and the second made up of a second material also having a high energy gap. The base ohmic contact is deposited on the first layer of the emitter. The invention also relates to the transistors obtained.

Abstract: A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by barrier layers comprising wide bandgap material (18) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a N-type drain region (22b). Each channel is also coupled to an N-type source region (25b). With appropriate gate bias on a gate electrode (17), quantized energy levels in the channels (12, 14, 16) are aligned to provide self-doping by electrons in the valence band of the P-channel (14) moving to the conduction band of the N-channels (12, 16) providing peak channel conductivity. At higher gate bias, one of the N-channels (12) becomes non-conductive creating a negative resistance region.

Abstract: A metal plane support structure of a semiconductor device multi-layer lead frame having one or more metal planes, of different types, arranged in stacked and aligned relationship with and adhered to a corresponding lead frame. Metal planes of a common type are defined in a corresponding metal strip, at longitudinally spaced positions, the metal strip having a pair of side rails along the longitudinal edges thereof, integral support bars extending transversely of the side rails and interconnecting the metal planes to the side rails and section bars extending between and integrally interconnecting the side rails, each section bar disposed between two adjacent metal planes. Separating portions are formed in aligned relationship in the support bars and section bars. The lead frames are defined, further, at longitudinally spaced positions corresponding to the spacing of the metal planes, in a further metal strip having a smaller transverse dimension than that of each metal plane strip.

Abstract: A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by barrier layers comprising wide bandgap material (18) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a P-type drain region (22b). Each channel is also coupled to an N-type source region (25b). With appropriate gate bias on a gate electrode (17), quantized energy levels in the channels (12, 14, 16) are aligned providing peak current flow by electrons tunneling from the conduction band of one or more N-channels (12, 16) to the valence band of the P-channel (14).