Abstract: A silicon nitride film 2 is formed on a GaAs substrate 1 and patterned to selectively expose the GaAS substrate surface in uniformly distributed areas having a width of not greater than 1 .mu.m. A non-doped GaAs buffer layer is grown on the GaAs substrate to completely cover the silicon nitride film. Then, a semiconductor multilayer structure including a non-doped GaAs layer is formed on the non-doped GaAs buffer layer. When a semiconductor integrated circuit device is manufactured using this semiconductor substrate, side gate effect can be effectively reduced due to the existence of the silicon nitride pattern and the buffer layer.

Abstract: Apparatus including a diamond semiconductor material bipolar transistor having associated therewith a distally disposed iso-collector. The iso-collector, when operated with a suitable voltage, provides a communicating electric field to the bipolar transistor collector which, in concert with a voltage coupled to the transistor base places the apparatus in an ON mode to induce electrons to be emitted from the collector and to be subsequently collected at the iso-collector. An iso-base is optionally, distally disposed relative to the base of the bipolar transistor.

Abstract: A planar semiconductor device having a heavily doped channel stopper region of the first conductivity type and at least the following components: a Zener diode having the following regions, seen from an upper surface of the device, an upper diode region of the second conductivity type, a lightly doped first upper component region, of the first conductivity type, in which the upper diode region and the channel stopper region are formed at the upper surface, and a heavily doped lower component region of the first conductivity type; and a component having a second upper component region formed with the upper diode region in the first upper component region at the upper surface and having the same conductivity type as the upper diode region, the first upper component region, the lower component region, and a third upper component region of the first conductivity type and formed in the second upper component region at the upper surface of the device.

Abstract: In a semiconductor integrated circuit device having cells comprising circuit elements including MISFETs, and a multi-layer wiring structure, wirings of a first layer connected to semiconductor regions of the MISFETs (source and drain regions) are formed almost in the entire area over the regions to shunt the regions. Power supply wiring are formed of second layer wirings. First layer wirings and the semiconductor regions are connected through a plurality of contact holes. The power supply wirings are formed to cover at least part of the semiconductor regions. In accordance with another aspect, macro-cells are formed by basic cells, including a plurality of MISFETs with the direction of gate length aligned in a first direction, regularly arranged in the first direction and in a second intersecting direction.

Abstract: A semiconductor device having a rectangular COB substrate body, a die pad on the surface of the substrate body, a plurality of outer leads at the periphery of the substrate body, a plurality of wiring patterns on the surface of the substrate body connected to corresponding outer leads, a plurality of inner leads on the surface of the substrate body surrounding the die pad, connected to corresponding outer leads by the corresponding wiring patterns, and arranged in a substantially rectangular shape having sides, each respectively forming a predetermined acute angle with respect to a corresponding side of the substrate body whereby intervals between adjacent wiring patterns are longer than a predetermined length, a semiconductor chip having a plurality of electrode pads and mounted on the die pad, and a plurality of wires establishing electrical connections between the plurality of electrode pads of the semiconductor chip and corresponding inner leads.

Abstract: An infrared imaging device includes a first conductivity type first semiconductor layer having a small energy band gap, a first conductivity type second semiconductor layer have a larger energy band gap and disposed on the first semiconductor layer, a light receiving region of the second conductivity type in the second semiconductor layer and extending into the first semiconductor layer, a second conductivity type region in the second semiconductor layer spaced from the light receiving region, an insulating layer on the second semiconductor layer, and an MIS electrode on the insulating layer between the light receiving region and the second conductivity type region. Recombination of signal charges produced by incident light in the light receiving region and leakage current at the surface of the second semiconductor layer at the light receiving region are reduced. In addition, the numerical aperture of the light receiving region is increased.

Abstract: A contact structure of a semiconductor device comprises a lamination of at least first insulating film, first conductive film and second insulating film formed in that order a through hole formed to penetrate through at least the first insulating film and the first conductive film so that a cross-section of the first conductive film is exposed to the through-hole and a second conductive film formed on an inner surface of the through-hole so that the second conductive film electrically contacts with the cross-section of the first conductive film.

Abstract: This invention relates to a monolithic IC having a PIN photodiode and an n-p-n bipolar transistor formed on a single semiconductor (silicon) substrate. In fabricating such IC, it is important to electrically isolate the photodiode and the bipolar transistor. In addition it is necessary to make the surface of the substrate flat. According to this invention, the inter-device isolation between the above-described two devices is attained by forming two epitaxial layers on the silicon substrate, forming trenches in the layers, and burying silicon dioxide in the trenches. In the monolithic IC according to this invention wiring capacity is small, and high-speed performance becomes possible. A p-type buried-layer is formed below the bipolar transistor to thereby prevent punch through between the bipolar transistor and other devices. Also this invention provides the process for fabricating a planar type bipolar transistor suitable to fabricate the monolithic IC and also provides a PIN photodiode of a new structure.

Abstract: A light-emitting diode of GaN compound semiconductor emits a blue light from a plane rather than dots for improved luminous intensity. This diode includes a first electrode associated with a high-carrier density n.sup.+ layer and a second electrode associated with a high-impurity density i.sub.H -layer. These electrodes are made up of a first Ni layer (110 .ANG. thick), a second Ni layer (1000 .ANG. thick), an Al layer (1500 .ANG. thick), a Ti layer (1000 .ANG. thick), and a third Ni layer (2500 .ANG. thick). The Ni layers of dual structure permit a buffer layer to be formed between them. This buffer layer prevents the Ni layer from peeling. The direct contact of the Ni layer with GaN lowers a drive voltage for light emission and increases luminous intensity.

Abstract: A lead frame assembly comprises a lead frame having cantilevered leads. Combined with the lead frame is a rigid, elongated base member having a U-shaped cross-section and laterally outwardly extending flanges at the upper ends of side walls of the base member. The leads of the lead frame overlie the base member flanges and are bonded to conductive paths on the flanges which extend along the flanges, along the base member side walls and onto the bottom wall of the base member. In use, a semiconductor chip is mounted on the bottom wall and wire bonded to respective ones of the conductive paths. Two base members can be used in flange-to-flange contacting relationship to provide a tubular enclosure for the chip.

Abstract: A ceramic hermetic package is provided having conductive material bonded into apertures in the ceramic housing that connect with a die mounted on a thin substrate through wire and pad connections. The substrate has a heat sink affixed to the bottom and electrical connections are formed on the opposite face of the package from the heat sink so that the encased semiconductor may be mounted on circuit boards in either a vertical position or in a position where the heat sink is horizontal but facing upward.

Abstract: Disclosed herein is a semiconductor device having a substrate, an insulating layer covering the substrate, a plurality of wiring layer formed on the insulating layer, each wiring layer having a top surface and a side surface, and a sidewall insulating film formed on and along the side surface of each of the wiring layers. The sidewall insulating film suppresses a hillock projecting from the side surface of each wiring layer.

Abstract: A bipolar transistor includes a substrate, an insulating layer formed on the substrate, and a semiconductor layer having a bottom surface and side surfaces surrounded by the insulating layer. The semiconductor layer includes a collector region formed in a first surface portion of the semiconductor layer, and a collector lead region having a concentration higher than that of the collector region. The collector read region includes a silicon single crystal layer formed in a second surface portion of the semiconductor layer, and a polysilicon layer having side surfaces surrounded by the silicon single crystal layer. A base region is formed on the collector region, and an emitter region is formed in the base region.

Abstract: A semiconductor circuit device is disclosed in which an impurity ion implanted region is formed in a substrate, a Schottky junction type gate electrode is formed above the impurity ion implanted region, and a source electrode and a drain electrode are formed on both sides of the gate electrode. In this device, an InGaP barrier layer is formed between the substrate and the electrodes, a cap layer comprising a semiconductor free from In as a constituent is formed between the InGaP barrier layer and the electrodes, and the gate electrode is formed of a refractory metal.

Abstract: A semiconductor device such as a semiconductor acceleration sensor of an electrostatic capacity type and a method of manufacturing the same are disclosed, wherein a silicon layer is bonded to first and second glass layers by means of an anodic bonding process in such a manner as to be positioned between the first and second glass layers. The first glass layer has an overhung portion protruded from an edge of the second glass layer. At least an interconnection is formed between the silicon layer and the first glass layer and has a bonding pad positioned on the inner surface of the overhung portion of the first glass layer. Before the anodic bonding process, an anodic-bonding-inhibition-layer such as aluminum layer is positioned between a second glass wafer forming the second glass layer and a silicon wafer forming the silicon layer, and faces to a predetermined portion of a first glass wafer forming the first glass layer.

Abstract: A semiconductor device having a metalized via hole used when mounting and connecting semiconductor chips, such as microwave chips, digital chips, analog chips and the like, on a top portion of a metalized carrier substrate is described herein. Each chip includes electrical circuitry on a top portion thereof with the circuitry connected to one end of a transmission line. Another end of the transmission line is connected to a metalized via hole. The via hole passes from the top portion of the chip to a bottom portion of the chip. The chip when mounted on the substrate is positioned over the top portion of the substrate and lowered thereon either by hand or with a mechanical chip carrying device. The bottom portion of the metalized via hole is indexed over a top of one end of a transmission line on the top portion of the substrate with the indexing tolerance between the two interfacing surfaces in a range of 0.5 to 10 mils.

Abstract: A semiconductor device according to the present invention includes a lower conductive layer having a plurality of dummy conductive lines in addition to operative conductive lines. The operative and dummy conductive lines are connected to an electrode pad of upper conductive layer by through holes. The upper and lower conductive layers are insulated from each other by an interfacial insulation layer.

Abstract: A multilayer, high yield and high density integrated circuit (IC) chips interposer and the method of manufacture therefore. A thin polyimide film is circuitized with copper on both sides. One side may be reserved for power or ground with the opposite side being a signal plane. Adhesive is laminated over both sides covering the circuit patterns. Vias are drilled through at least one adhesive surface, and through the polyimide film. Metal (copper) is blanket sputtered to coat the via walls. Polymer Metal Conductive (PMC) paste is screened to at least partially fill the vias. The Blanket metal is sub-etched using the screened PMC as a mask. Layers are stacked to form the interposer with the PMC bonding the stacked layers together and electrically interconnecting between layers.

Abstract: A non-volatile memory includes a single transistor having a semiconductor substrate, source and drain diffusion layers formed on a surface of the semiconductor substrate, and a gate electrode provided on the semiconductor substrate with a gate insulating film interposed between them. The non-volatile memory further includes a programmable insulating film provided in self-alignment between the gate electrode and at least one of the source and drain diffusion layers and the programmable insulating film is broken down by a voltage applied to the gate electrode so as to execute programming.

Abstract: A field-effect structure formed on a substrate and comprising a channel with source and drain as well as a gate that is separated from the channel by an insulating layer. The channel is made of a high T.sub.c metal-oxide superconductor, e.g., YBaCuO, having a carrier density of about 10.sup.21 /cm.sup.3 and a correlation length of about 0.2 nm. The channel thickness is preferrable in the order of 1 nm. The superconductor is preferably a single crystalline and oriented such that the superconducting behavior is strongest in the plane parallel to the substrate. With a signal of a few volts applied to the gate, the entire channel cross-section is depleted of charge carriers whereby the channel resistance can be switched between a "zero resistance" (undepleted, superconducting) state and "very high resistance" (depleted state).