Patents Examined by Andrew M Lyons
  • Patent number: 11782814
    Abstract: Embodiments learn and visualize a software component and interface. Software code including a series of events can be received, where the series of events include calls to a software component and interface under test. Supplemental code can be injected into the received code. The software code with the injected supplemental code can be executed, where the executed supplemental code generates state data for the software component and interface. Based on the generated state data, a state diagram visualization can be generated that visualizes states and state transitions for the software component and interface under test given the series of events.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: October 10, 2023
    Assignee: Oracle International Corporation
    Inventors: Dharmalingam Ganesan, David M. Clifton
  • Patent number: 11782813
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine refined context for bug detection. At least one non-transitory machine-readable medium includes instructions that, when executed, cause at least one processor to at least classify a node on a graph, the graph to represent a computer program, the node to contain partial bug context corresponding to the computer program; identify a location of a software bug in the computer program, the location based on the node; determine a static bug context of the software bug using the location of the software bug; determine a dynamic bug context of the software bug using the location of the software bug; and determine a refined bug context based on a merge of the static bug context and the dynamic bug context.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Shengtian Zhou, Justin Gottschlich, Fangke Ye, Celine Lee, Jesmin Jahan Tithi
  • Patent number: 11782819
    Abstract: A user-annotated reference implementation identifies variable values generated by the reference implementation during its execution. A software implementation under analysis is executed. Variable values in the running memory of the program code of the software implementation under analysis, during its execution, are identified and copied. The variable values traced from the running memory of the program code are compared against the annotated variable values generated by the reference implementation, to determine a similarity between the program code under analysis, and the reference implementation. An output is generated that is indicative of whether the traced variables from the program code under analysis are the same as the annotated variable values generated by the reference implementation.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: October 10, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Nir Levy, Lee Stott, Ran Gilad-Bachrach
  • Patent number: 11775414
    Abstract: A device includes one or more processors configured to: receive source code including a section of source code associated with at least one bug or vulnerability; generate a formatted code section based at least partly on the section of source code associated with at least one bug or vulnerability; identify a matching patch model based on the formatted code section; provide the formatted code section to the matching patch model; receive a remedied code section from the matching patch model; and apply the remedied code section to the section of source code associated with at least one bug or vulnerability. Generating the formatted code section based at least partly on the section of source code associated with at least one bug or vulnerability includes: dividing the section of source code into sub-elements; associating type information to the sub-elements to generate tokens; and mapping each token to a unique identifier.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: October 3, 2023
    Assignee: RAM Laboratories, Inc.
    Inventors: John Darragh Geddes, Robert Michael McGraw
  • Patent number: 11742038
    Abstract: Exemplary embodiments provide wear spreading among die regions (i.e., one or more circuits) in an integrated circuit or among dies by using operating condition data in addition to or instead of environmental data such as temperature data, from each of a plurality of die regions. Control logic produces a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data wherein the operating condition data is based on at least one of the following operating characteristics: frequency of operation of the plurality of die regions, an operating voltage of the plurality of die regions, an activity level of the plurality of die regions, a timing margin of the plurality of die regions, and a number of detected faults of the plurality of die regions. The method and apparatus spreads wear among the plurality of same type of die regions by controlling task execution among the plurality of die regions using the die wear-out data.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 29, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Steven Raasch, Greg Sadowski, David A. Roberts
  • Patent number: 11726899
    Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: August 15, 2023
    Assignee: Synopsys, Inc.
    Inventors: Gagan Vishal Jain, Johnson Adaikalasamy, Alexander John Wakefield, Ritesh Mittal, Solaiman Rahim, Olivier Coudert
  • Patent number: 11720474
    Abstract: A method, system, or apparatus to debug software that is reorganized in memory is presented. A post-mortem debugging session is established by loading an executable code component corresponding to a packed binary file into memory. A randomly reorganized layout of the machine code corresponding to the blocks of the original source code is generated based on a transformation defined in a function randomization library corresponding to the blocks of original source code. A core dump file corresponding to the crash event associated with the executing of the executable code component and a debug data file that includes symbol table information to debug the blocks of the original source code are received. An updated debug data file is generated that includes symbol table information corresponding to the randomly reorganized layout. A debugger program is called with the executable code component, the core dump file, and the updated debug data file.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: August 8, 2023
    Assignee: RUNSAFE SECURITY, INC.
    Inventor: Mitchell Lee Souders
  • Patent number: 11714742
    Abstract: High level synthesis (HLS) begins with high-level specification of a problem, where behavior is generally decoupled from e.g., clock-level timing. Programming code can be run and debugged during functional simulation using debugging techniques. However, it is not possible to understand execution flow of register transfer level instructions (RTL) generated during RTL debug. Conventionally, it is challenging and not possible due to nature of debugging techniques which ignore printf statements in code for invocation. Systems and methods of present disclosure synthesize printf and/or scanf statements for generating debug messages in HLS code, wherein printf and/or scanf statements is/are included before/after function(s) in sections comprising instructions in code and synthesized as a block during run-time which communicate with host system and debug messages are generated for display on screen.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: August 1, 2023
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Mahesh Damodar Barve, Sunil Anant Puranik, Manoj Karunakara Nambiar, Swapnil Shashikant Rodi
  • Patent number: 11709757
    Abstract: Systems and methods provide for an integrated script development and script validation platform. The integrated script development and script validation platform archives data in a way such that the dependencies between contributions of code strings (e.g., script sets) are detected and recorded. That is, the systems and methods detect dependency branches in the script code of script sets. By doing so, the systems and methods may identify individual performance characteristics for a given script set as well as determine the overall impact on the application itself.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: July 25, 2023
    Assignee: Citibank, N.A.
    Inventors: Robin Jose Kurian, Joseph Julius Bosco Arockia Dass, Balaji Kobula Madhavan
  • Patent number: 11709765
    Abstract: Aspects of the disclosure relate to generating test cases based on voice conversation. In some embodiments, a computing platform may receive voice data associated with an agile development meeting. Subsequently, the computing platform may identify, using a natural language processing engine, context of one or more requirements being discussed during the agile development meeting. Based on identifying the context of the one or more requirements being discussed during the agile development meeting, the computing platform may store context data into a database. Next, the computing platform may map the context data to a corresponding task item of a software development project. Thereafter, the computing platform may identify one or more test cases to be generated. Then, the computing platform may cause the identified test cases to be executed.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: July 25, 2023
    Assignee: Bank of America Corporation
    Inventors: Kiran Sudhir Raja, Udaya Kumar Raju Ratnakaram, Arnold Teen Absalom, Bibhu Ranjan Sahoo
  • Patent number: 11709763
    Abstract: Systems and methods are disclosed herein for improving data migration operations including testing and setup of computing environments. In one example, the method may include receiving data for one or more application programming interfaces (APIs). The method may further include generating one or more tests to test the one or more APIs in a first computing environment, testing the APIs, storing the results in a database, and performing a change data capture operation. The method may further include augmenting the one or more tests with the CDC data to generate an updated test. The method may further include testing, using the updated test, a second set of the one or more APIs and comparing the test results. The method may also include outputting a confidence score indicating a correlation between the first environment and the second environment.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: July 25, 2023
    Assignee: Capital One Services, LLC
    Inventors: Raghuram Madiraju, Palak Mathur, Maz Jawed Baig, Devi Kiran Gonuguntla, Ajmal Karuthakantakath
  • Patent number: 11704133
    Abstract: Disclosed herein are enhancements for deploying application in an edge system of a communication network. In one implementation, a runtime environment identifies a request from a Hypertext Transfer Protocol (HTTP) accelerator service to be processed by an application. In response to the request, the runtime environment may identify an isolation resource to support the request, initiate execution of code for the application, and pass context to the code. Once initiated, the runtime environment may copy data from the artifact to the isolation resource using the context and return control to the HTTP accelerator service upon executing the code.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: July 18, 2023
    Assignee: Fastly, Inc.
    Inventors: Tyler McMullen, Jonathan Foote, Patrick Hickey, Jason Cook
  • Patent number: 11693760
    Abstract: A method, system, or apparatus to debug software that is reorganized in memory is presented. An interactive debugging session is established with an executable code component corresponding to a packed binary file includes machine code that corresponds to blocks of original source code. A randomly reorganized layout of the machine code is generated in memory based on a transformation defined in a function randomization library. An in-memory object file is created by using a debug data component corresponding to the packed binary file. The debug data component includes symbol table information to debug the blocks of the original source code generated prior to the randomly reorganized layout. The symbol table information is updated based on the randomly reorganized layout of the machine code, and the debugger program is instructed to load the in-memory object file with the updated symbol information to debug the blocks of the original source code.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: July 4, 2023
    Assignee: RUNSAFE SECURITY, INC.
    Inventor: Mitchell Lee Souders
  • Patent number: 11675691
    Abstract: A framework and a method for ad-hoc batch testing of APIs are provided, where batches of API calls are dynamically generated directly through the framework according inputs identifying the required tests and the sources of the test data, rather than through execution of prewritten test scripts that explicitly write out the test API calls in preset sequences. When performing the validation for an API test, a test payload is generated for the test, an endpoint is called using the test payload to obtain the response used for validation, where generating the test payload includes determining an API reference corresponding to the test, obtaining relevant data from the test data according to a reference key in the test, generating input assignment operations for one or more input parameters in the API reference according to the relevant data, and generating an API call based on the API reference.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: June 13, 2023
    Assignee: PROKARMA, INC.
    Inventors: Ramanathan Sathianarayanan, Krishna Bharath Kashyap
  • Patent number: 11669440
    Abstract: A prioritized list of recommended disk images is created by providing software artifacts associated with a virtual network function that has access to a set of system libraries. Validation tests for the software artifacts are provided in the virtual network function is instantiated. The validation tests are run in the call invocations from the virtual network function to the set of system libraries is monitored. The system call invocations generated by the validation tests are analyzed and a list of required libraries based on system call invocations generated by the validation test is created. A list of recommended disk images with performance metrics are created and communicated to a developer.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: June 6, 2023
    Assignee: AT&T Intellectual Property I, L.P.
    Inventor: Julius Mueller
  • Patent number: 11650906
    Abstract: Embodiments disclosed herein relate to methods, systems, and computer programs for verifying that data incorporated into a computer program is current. The methods, systems, and computer programs compare a source identifier status code associated with the data to a current source identifier status code at the location where the data was obtained. The methods, systems, and computer programs include at least one validation function which determines the validity of the data according to selected parameters. If the source identifier status code and current source identifier status code match and the at least one validation function determines the data is valid, an executable computer program incorporating the data and one or more functions is produced as output.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 16, 2023
    Assignee: Cotiviti, Inc.
    Inventors: Christopher Taylor Creel, Mykel Alvis
  • Patent number: 11640352
    Abstract: Disclosed is a method, a device, a system and/or a manufacture of testing software and/or computing hardware design through test fragmentation into one or more discrete computing environments. In one embodiment a method for efficient testing with a test fileset includes initiating a new instance of an operation filesystem and copying a software application, a script, a computer hardware design, and/or a circuit design to be tested into the operation filesystem to define a workspace data. The method defines a discrete environment that is a computing container and/or a virtual computer, the assigns the discrete environment a processing power and/or memory allocation from a computing resources pool and clones a workspace master to generate a workspace clone. The method then extracts a test script from the test fileset, executes the test script within the workspace clone, and returns the resources to the computing resources pool.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: May 2, 2023
    Assignee: Methodics, Inc.
    Inventors: Vishal Moondhra, Peter Theunis
  • Patent number: 11551990
    Abstract: Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: January 10, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: David A. Roberts, Greg Sadowski, Steven Raasch
  • Patent number: 11537394
    Abstract: Systems and methods for estimating a random distribution for an overall metric for a composite node, the composite node comprising a plurality of nodes. For each data atom of a plurality of data atoms being input to the composite node, and for each node of the plurality of nodes, at least one value may be generated for a per-node metric with respect to the data atom. A value for the overall metric with respect to the data atom may be generated based on the per-node metric values of the plurality of nodes. At least one parameter of the random distribution for the overall metric for the composite node may be estimated based on the overall metric values with respect to the plurality of data atoms.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: December 27, 2022
    Assignee: F0cal, Inc.
    Inventor: Brian F. Rossa
  • Patent number: 11520633
    Abstract: A method and system for thread aware, class aware, and topology aware memory allocations. Embodiments include a compiler configured to generate compiled code (e.g., for a runtime) that when executed allocates memory on a per class per thread basis that is system topology (e.g., for non-uniform memory architecture (NUMA)) aware. Embodiments can further include an executable configured to allocate a respective memory pool during runtime for each instance of a class for each thread. The memory pools are local to a respective processor, core, etc., where each thread executes.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: December 6, 2022
    Assignee: Rambus Inc.
    Inventor: Keith Lowery