Patents Examined by Andrew Russell
  • Patent number: 9571396
    Abstract: A system may include receiving a packet, of a packet stream, including control tags in a header portion of the packet and classifying each of the control tags into a category selected from a set of possible categories. The set of possible categories may include an unambiguous interposable (UI) category that is assigned to a control tag that corresponds to an unambiguous parsing interpretation and that is interposable within a sequence of the control tags, and an ambiguous interposable (AI) category that is assigned to a control tag in which the control tag has an ambiguous parsing interpretation and in which the control tag is interposable within the sequence of the control tags. The method may further include determining parsing operations to perform for the packet based on the classified categories of the control tags and based on the packet stream of the packet.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: February 14, 2017
    Assignee: Juniper Networks, Inc.
    Inventors: David Talaski, Avanindra Godbole, Jean Marc Frailong, Fanyun Kong
  • Patent number: 9563556
    Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: February 7, 2017
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 9558040
    Abstract: A memory management system is described herein that receives information from applications describing how memory is being used and that allows an application host to exert more control over application requests for using memory. The system provides an application memory management application-programming interface (API) that allows the application to specify more information about memory allocations that is helpful for managing memory later. The system also provides an ability to statically and/or dynamically analyze legacy applications to give applications that are not modified to work with the system some ability to participate in more effective memory management. The system provides application host changes to leverage the information provided by applications and to manage memory more effectively using the information and hooks into the application's use of memory.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: January 31, 2017
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Steven Maillet, Michael Hall, James Larus, Jeremiah C. Spradlin
  • Patent number: 9542126
    Abstract: Methods and structure are provided for defining span sizes for Redundant Array of Independent Disks (RAID) systems. One embodiment is a RAID controller that includes a control system and a span manager. The control system is able to identify storage devices coupled with the controller and is able to receive input requesting the creation of a RAID logical volume. The span manager is able to define multiple RAID spans to implement the volume, each span comprising one or more of the coupled storage devices, at least one of the spans including a different number of drives than at least one other span.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: January 10, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: David Moon, Anuj K. Jain, Gerald E. Smith, Naveen Krishnamurthy, Subhankar Mukherjee
  • Patent number: 9535835
    Abstract: A method for managing a storage device including determining whether the storage device includes a non-volatile cache, scanning for a clear cache instruction received from a computing machine, and clearing the non-volatile cache on the storage device in response to authenticating the clear cache instruction.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: January 3, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Leonard E. Russo, Walter A. Gaspard, Walter W. Bellamy
  • Patent number: 9389673
    Abstract: A method includes entering a hibernation mode in a data storage device with a controller, a non-volatile memory, and a volatile memory having a first portion and a second portion. The hibernation mode is entered by copying, to the second portion, data that is in the first portion and that is flagged to remain available at the volatile memory during the hibernation mode, and powering off the first portion while maintaining power to the second portion.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: July 12, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Daniel Zvi Yerushalmi, Yaniv Iarovici
  • Patent number: 9218206
    Abstract: A memory management system is described herein that receives information from applications describing how memory is being used and that allows an application host to exert more control over application requests for using memory. The system provides an application memory management application-programming interface (API) that allows the application to specify more information about memory allocations that is helpful for managing memory later. The system also provides an ability to statically and/or dynamically analyze legacy applications to give applications that are not modified to work with the system some ability to participate in more effective memory management. The system provides application host changes to leverage the information provided by applications and to manage memory more effectively using the information and hooks into the application's use of memory.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: December 22, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jeremiah C. Spradlin, Galen Hunt, Akshay Johar, Steven Maillet
  • Patent number: 9189195
    Abstract: Systems and methods are described here to provide a degree or level of certification to a resident application such as an operating system, e.g., Linux®. In a Linux® implementation, the operating system provides a robust environment including many seasoned communication stacks, e.g., TCP/IP, USB, and the like. However, Linux® is not certified to the level necessary to be a part of many avionics applications. To eliminate the need to certify all of such an operating system, such certification being highly costly, the avionics application itself may be protected so that the operating system cannot alter the application's operating environment, e.g., application code and data, once the application is loaded and running. In this case, only the application requires certification at the highest level, and not the operating system such as Linux®.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: November 17, 2015
    Assignee: SANDEL AVIONICS, INC.
    Inventor: Gerald J. Block
  • Patent number: 9183000
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage able to hold data, a temperature measurement section configured to measure the temperature of the semiconductor storage, a temperature varying section configured to change the temperature of the semiconductor storage, and a control circuit including a transmitter configured such that data received from a host is transferred to the semiconductor storage, and a temperature storage configured to store temperature information received from the temperature measurement section.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 10, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Ichida, Hiroshi Sukegawa, Naohiro Matsukawa
  • Patent number: 9185180
    Abstract: A system operable to: receive a request for an application unit from a first device; generating a key for the application unit; look up segment cache indices corresponding to the application unit, according to the key; and determine whether the segment cache indices are available. Where the segment cache indices are available, the system may retrieve a segment cache using the segment cache indices; and then retrieve the application unit using the retrieved segment cache. Otherwise, where the segment cache indices are not available, the system may communicate the request to a second device to receive a response from the second device including the segment indices. Further, the system may receive the response from the second device; store a segment index sequence for the application unit in an application optimizer cache based on the response; and retrieve the application unit via the segment index sequence.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: November 10, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Hariharan Ananthakrishnan, Srinivasan Santhanam
  • Patent number: 9165005
    Abstract: Method and apparatus for storing records in non-uniform access memory. In various embodiments, the placement of records is localized in one or more regions of the memory. This can be accomplished utilizing different ordered lists of hash functions to preferentially map records to different regions of the memory to achieve one or more performance characteristics or to account for differences in the underlying memory technologies. For example, one ordered list of hash functions may localize the data for more rapid access. Another list of hash functions may localize the data that is expected to have a relatively short lifetime. Localizing such data may significantly improve the erasure performance and/or memory lifetime, e.g., by concentrating the obsolete data elements in one location. Thus, the two or more lists of ordered hash functions may improve one or more of access latency, memory lifetime, and/or operation rate.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 20, 2015
    Assignee: SimpliVity Corporation
    Inventors: Arthur J. Beaverson, Paul Bowden, Sowmya Manjanatha, Jinsong Huang
  • Patent number: 9146875
    Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data tracks, and a non-volatile semiconductor memory (NVSM) comprising a plurality of memory segments. When a life remaining of the NVSM falls below a threshold, the NVSM is marked as read only. When a write command is received from a host including write data, and when the NVSM is marked as read only, the write data is written to the disk and a corresponding memory segment in the NVSM is invalidated.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: September 29, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: William B. Boyle, Mei-Man L. Syu, William C. Cain
  • Patent number: 9146679
    Abstract: A primary physical storage device has effectively limitless apparent free space. Responsive to receiving a request to dynamically allocate an amount of desired free space on the primary device to store new data on the primary device, and responsive to determining that an amount of actual free space on the primary device is insufficient to permit such allocation, existing data stored on the primary device is moved to a secondary storage device. The first existing data appears to still be stored on the primary device. Responsive to receiving a request to retrieve existing data from the primary device, and to determining that the existing data has been moved to the secondary device, the existing data is moved back to the primary device. The existing data was originally stored on the primary device, and is currently stored on the primary device or has been moved to the secondary device.
    Type: Grant
    Filed: June 18, 2011
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Martin, Dustin A. Helak, Jason Webster
  • Patent number: 9135158
    Abstract: Systems and methods are disclosed in which a derived table can inherit a growth pattern from a template table. A growth pattern is used to define how memory is allocated to a table as the table grows. The derived table can inherit the growth pattern defined by its template table or it can provide an override growth pattern. Inheritance of the growth pattern can be performed by explicit copying or by reference or link. Growth patterns can be edited, and the edits can be applied universally or locally.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: September 15, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Brett A. Shirley, Marcus E. Markiewicz
  • Patent number: 9122616
    Abstract: A method for performing dynamic configuration includes: freezing a bus between a portion of a dynamic configurable cache and at least one of a plurality of cores/processors by pending a request from the at least one of the cores/processors to the portion of the dynamic configurable cache during a bus freeze period, wherein the plurality of cores/processors are allowed to access the dynamic configurable cache and the at least one of the plurality of cores/processors is allowed to access the portion of the dynamic configurable cache; and adjusting a size of the portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for the at least one of the plurality of cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: September 1, 2015
    Assignee: MEDIATEK INC.
    Inventors: You-Ming Tsao, Hsueh-Bing Yen
  • Patent number: 9122417
    Abstract: A network attached storage device may include at least one storage device, a network connection coupling the at least one storage device to a network and a processor coupled to the at least one storage device and to the network connection. The processor may be configured to monitor a plurality of operating parameters of the network attached storage; determine a state of a network attached storage based on at least two of the monitored plurality of operating parameters of the network attached storage; determine a current level of protection from among a predetermined plurality of levels of protection based on the determined state of the network attached storage, and provide an indication of the determined level of protection afforded by the network attached storage.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: September 1, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventor: Stephen A. Hellwege
  • Patent number: 9122614
    Abstract: A modular block allocator receives a cleaner message requesting dirty buffers associated with an inode be cleaned. The modular block allocator provides at least one bucket cache comprising a plurality of buckets, wherein each bucket represents a plurality of free data blocks. The dirty buffers are cleaned by allocating the data blocks of one of the buckets to the dirty buffers. The allocated data blocks are mapped to a stripe set and when the stripe set is full, the stripe set is sent to a storage system. In one embodiment of the invention, a modular block allocator includes a front end module and a back end module communicating with each other via an application programming interface (API). The front end module contains write allocation policies that define how blocks are laid out on disk. The back end module creates data structures for execution of the policies.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 1, 2015
    Assignee: NetApp, Inc.
    Inventors: Ram Kesavan, Mrinal K. Bhattacharjee, Sudhanshu Goswami
  • Patent number: 9116820
    Abstract: The specification and drawings present a new apparatus, method and software related product for using a cache/central cache module/device (instead of e.g., system DRAM) which can serve multiple memory modules/devices. Each memory/IO module/device connected to the same memory network (e.g., via hub, bus, etc.) may utilize memory resources of this cache module/device either in a fixed manner using pre-set allocation of resources per the memory module/device, or dynamically using run-time allocation of new resources to an existing module/device per its request or to a new module/device connecting to the memory network (e.g., comprised in a host device) and possibly requesting memory resources.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: August 25, 2015
    Assignee: Memory Technologies LLC
    Inventor: Kimmo J. Mylly
  • Patent number: 9111648
    Abstract: A method includes, for a memory die including at least first and second memory planes, each including multiple physical memory blocks, holding a definition of a redundancy mapping between first memory blocks in the first memory plane and respective second memory blocks in the second memory plane, such that a physical separation on the die between each first physical memory block and a corresponding second physical memory block meets a predefined criterion. Data is stored in one or more first physical memory blocks in the first memory plane. Redundancy information is stored relating to the data in one or more second physical memory blocks in the second memory plane that are mapped by the redundancy mapping to the one or more first physical memory blocks.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: August 18, 2015
    Assignee: Apple Inc.
    Inventors: Avraham Poza Meir, Alexander (Sasha) Paley
  • Patent number: 9111649
    Abstract: There is provided a semiconductor device which is simple in configuration and resistant to tampering. A user input unit receives an authentication code input by a user. A CPU determines whether a user's access is legal based on the input authentication code and activates an enable signal if the user's access is legal. A normal row decoder decodes the row address specified by the CPU and selects a normal memory cell of any row based on the result of decode. A redundancy row decoder prohibits the selection by the normal row decoder when the specified row address agrees with the row address of a predetermined normal memory cell only if the enable signal is activated and selects a redundant memory cell of any row.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: August 18, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshifumi Kawamura, Hirofumi Nakano, Hiroyuki Kawai