Abstract: An OR array including a first multiplicity of OR devices, to which a second multiplicity of product term signals are variably distributed. Some product term signals are distributed to four OR devices, other product term signals are distributed two or three OR devices, and still other product term signals are distributed to only one OR device.

Abstract: The present invention provides a level converting circuit comprising: a differential output transistor circuit for amplifying a difference between two mutually complementary input logic signals; a first output transistor circuit for outputting an inverted output logic signal based on a signal output by the differential output transistor circuit; and a second output transistor circuit for outputting an uninverted output logic signal based on a signal output by the differential output transistor circuit, wherein the first output transistor circuit further comprises first and second field-effect transistors and the second output transistor circuit further comprises third and fourth field-effect transistors. The differential output transistor circuit comprises a combination of first, second, third, fourth and fifth bais components which are each resistive element or a field-effect transistors.

Abstract: A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith.

Abstract: The generation of a controlled voltage signal as a buffer control signal for an output driver provides for relatively less delay for a high output enable access for an output buffer. As the output buffer undergoes the transition from a deselected state to a selected state to generate an output signal corresponding to a high input signal, a first voltage level is generated at a node and output as the control signal for the output driver, providing for an initial pull-up transition for the output signal. A second voltage level is subsequently generated at the node and output as the control signal for the output driver, providing for a steady-state voltage level for the high output signal.

Abstract: A logic state detector that indicates a floating state of a tri-state logic circuit. The logic state detector generates first and second binary logic signals at a pair of output terminals. A first unique combination of the values of the output signals denotes that the input signal represents a logic low, a second unique combination denotes that the input signal represents a logic high, and a third unique combination denotes that the input signal is floating.

Abstract: An elementary cell uses single-flux-quanta as two-valued logic propagation signals and is effective for Constructing asynchronous superconducting logic circuits. The elementary cell comprises one OR circuit section and one AND circuit section. Input pulses applied to two input terminals of the elementary cell are split at signal splitting sections in the elementary cell and applied to both inputs of the OR circuit section and both inputs of the AND circuit section. The output of the OR circuit section is defined as the OR output of the elementary cell. A first arrival pulse memory section is provided in the AND circuit section and when one of two input pulses input to the two input terminals of the AND circuit section arrives before the other, this fact is recorded in the first arrival pulse memory section as logical "1".

Abstract: An input signal is inverted by an inverter in the first stage and an n-channel MOS transistor on the pull up side in a driver is driven, while an output signal of the inverter in the first stage is inverted by an inverter in the next stage and an n-channel MOS transistor on the pull down side is driven. A driving signal is output from a connection point between the n-channel MOS transistor on the pull up side and the n-channel MOS transistor on the pull down side, and an output transistor is driven by the driving signal. Since a gate voltage of the output transistor increases only by a value of a power supply voltage Vdd minus threshold voltage V.sub.T, a rise time and a fall time of a gate potential can be reduced, resulting in improvement in the duty cycle.

Abstract: The power consumption by a combinational logic circuit having primary input and output terminals is reduced. The constituent gates of the combinational logic are clustered in terms of the operating voltage levels thereof. First, the gates driven with the highest operating voltage are clustered just adjacent to the primary input terminals. Next, the gates driven with the next higher voltage are clustered adjacent to the primary input terminals only through the gates driven with the highest voltage, followed by repetition of the same clustering procedure in the order of the operating voltage level. Finally, the gates driven with the lowest operating voltage are clustered Just adjacent to the primary output terminals.

Abstract: An interface circuit includes an input current limiting circuit for limiting a current of an input signal fed from a preceding circuit, thereby outputting the current-limited signal to a following circuit which is constituted using a MES type transistor. The interface circuit also includes a level shifting circuit supplied with a first higher power supply voltage and a lower power supply voltage, for converting a level of the current-limited signal into a logic level of the following circuit which is supplied with a second higher power supply voltage. The interface circuit further includes a level judging circuit connected between the input current limiting circuit and the level shifting circuit, for judging a logic threshold level of the input signal based on a predetermined level reference voltage. By the constitution, it is possible to adapt the interface circuit for connection to the following circuit constituted using MES type transistors.

Abstract: A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.

Abstract: A semiconductor device by which a circuit having the same functions as those of the conventional circuit is realized with a very small number of elements, and complex logical functions can be designed simply, and further, its layout is also possible. A semiconductor device made up of at least one neuron MOS transistor having a gate electrode provided in a potentially floating state in a portion for isolating a source and drain region via a first insulation film, and plural control electrodes which are capacitively coupled to the floating gate electrode via a second insulation film, is characterized in that the first signal is inputted to a first control gate electrode of the first neuron MOS transistor, the first signal is inputted to a first inverter comprising one or more stages, and the output of the first inverter is inputted to a second control gate electrode which is one of the plural control gate electrodes other than the first control gate electrode.

Abstract: In a field programmable gate array, a plurality of wire segments extend parallel to each other between two logic cells. Some of the wire segments extend to logic cell inputs and others to logic cell outputs. A power wire extends perpendicular to the wire segments and crosses each of the wire segments. Antifuses are disposed to couple the input wire segments to the power wire but no antifuses are disposed between the output wire segments and the power wire.

Abstract: Disclosed is a semiconductor integrated circuit which have a pair of transistors Q11, Q12 with a first polarity being differentially inputted with first logical values A(+) and A(-), a first constant current source I11 for driving the pair of transistors with the first polarity, two pairs of transistors Q13, Q14 and Q15, Q16 with a second polarity, each of the two pairs of transistors being differentially inputted with second logical values B(+) and B(-) and being connected to a drain of each of the pair of transistors with the first polarity, a second and third constant current sources I12, I13 for driving the two pairs of transistors, respectively, and load resistors R11, R12 which are connected to the two pairs of transistors, respectively.

Abstract: An integrated circuit is presented having a driver circuit programmable to produce a variety of output voltages and conductive to the voltage levels of circuits interfaced by the integrated circuit. The integrated circuit includes programmable pullup and pulldown functions. The integrated circuit may be configured into an application having devices powered by a power supply voltage which is substantially larger than the voltage supplying the core section of the integrated circuit. Additionally, the present integrated circuit may be configured into other applications having devices powered by a power supply voltage substantially similar to the voltage supplying the integrated circuit core section. The present integrated circuit therefore retains utility for a large variety of applications. The pullup and pulldown transistors may be programmed to provide a resistive one, resistive zero, or neither.

Abstract: An apparatus includes an IC chip with a signal transmitter and an IC chip with a signal receiver, both chips being mounted on a printed circuit board and being connected via conductors on the board. The signal transmitter has a voltage-current converter and a high output impedance current amplifier. The signal receiver has a current-voltage converter. The voltage-current converter converts the voltage of the digital signal to current which in turn is amplified by the high output impedance current amplifier. The amplified current flows via the conductors in the receiver. The digital signal is transferred via the conductors on the current basis. Due to the transmission of the digital signal of current from the signal transmitter to the signal receiver via the conductors, signal spikes while transmitting are reduced and noise immunity is improved. Also, EMI (electromagnetic interference) emission is reduced and power dissipation is small.

Abstract: An apparatus includes an IC chip with a signal transmitter and an IC chip with a signal receiver, both chips being mounted on a printed circuit board and being connected via conductors on the board. The signal transmitter has a voltage-current converter and a high output impedance current amplifier. The signal receiver has a current-voltage converter. The voltage-current converter converts the voltage of the digital signal to current which in turn is amplified by the high output impedance current amplifier. The amplified current flows via the conductors in the receiver. The digital signal is transferred via the conductors on the current basis. Due to the transmission of the digital signal of current from the signal transmitter to the signal receiver via the conductors, signal spikes while transmitting are reduced and noise immunity is improved. Also, EMI (electromagnetic interference) emission is reduced and power dissipation is small.

Abstract: A data transfer circuit device including a data transfer circuit, a latch control circuit and a data latch circuit. The data transfer circuit outputs data therefrom in response to an externally supplied transfer signal. The latch control circuit generates a data latch signal, based on the transfer signal and a latch control signal. The data latch circuit latches the data supplied from the data transfer circuit, based on the data latch signal, and outputs the latched data as output data. When the data is being switched, the latch control circuit prevents the data latch signal from being supplied to the data latch circuit.

Abstract: An improved CMOS driver circuit for driving a fast, single-ended, wired-or bus architecture. The driver circuit provides a user-selectable active deassertion assist feature which assists a passive terminator circuit in quickly pulling-up a data or control bus line. The resulting driver circuit provides greater noise immunity to negative voltage transients that result from impedance mismatches caused by poor cable design configurations.

Abstract: A circuit and method are provided for reducing the DC power consumption of clocked ratioed digital logic circuits. The circuit includes switching circuitry designed to analyze the voltage transitions of a ratioed digital logic circuit and based on such transitions, control the DC current flow through the entire circuit. Through the regulation of DC current flow through a digital logic circuit, the present invention reduces the detrimental effects of hot-electron effects and electromigration concerns which cause digital circuitry to fail. The circuit and method are illustrated by way of a ratioed logic NOR function employing MOSFET technology.

Abstract: A clock regeneration circuit capable of obtaining clocks each having an arbitrary duty. The clock regeneration circuit comprises a first D-type flip-flop having a clock terminal for receiving an input clock signal from an input terminal, and a data input terminal for receiving data of an H level, a second D-type flip-flop having a clock terminal for receiving the input clock signal from the input terminal, and a data input terminal for receiving data of an H level, a first delay circuit which receives an output from an output terminal of the first D-type flip-flop and outputs an output thereof to the reset terminal of the first D-type flip-flop, and a second delay circuit which receives the output from an output terminal of the first D-type flip-flop and outputs an output to a reset terminal of the second D-type flip-flop, wherein an output clock signal is outputted from an output terminal of the second D-type flip-flop to an output terminal.