Abstract: A memory (20) has a read cycle and a write cycle. During the read cycle, differential data signals, corresponding to data provided by a selected memory cell, are superimposed on a first common mode voltage and provided to data output buffers (70-73). During the write cycle, differential data signals on read global data lines (61-62) are equalized at a second common mode voltage and data output buffers (70-73) are disabled. Output enable circuit (74) provides an output enable signal halfway between the first and second common mode voltages. Data output buffers (70-73) are enabled at the beginning of the read cycle when the differential data signals cross the output enable signal as they transition from the second common mode voltage to the first common mode voltage. Enabling data output buffers (70-73) in this way greatly relaxes output enable timing constraints.

Abstract: A write control circuit is provided for supplying a gate of an n-channel enhancement-type writing transistor with a voltage corresponding to data when the data is written. The circuit comprises a reference potential-generation circuit, a differential amplifier, and a feedback circuit. The reference potential-generation circuit generates a reference potential substantially equal to the upper limit of that high level of each of the bit lines which is assumed at the time of writing. The differential amplifier has an input terminal to be supplied with the reference potential. A write voltage serving as an operation voltage is applied to the amplifier. The feedback circuit is connected between the other input terminal and output terminal of the differential amplifier.

Abstract: In the semiconductor memory composed of divided dynamic memory cell arrays, when a drive signal is supplied to a word line selected by a row decoder, data stored at the memory cells connected to the word line are transferred to bit lines, respectively. A change in potential at the bit line pair is amplified by the sense amplifier to completely read the data. To prevent the bit line pairs from being sensed erroneously due to fluctuation of the timings at which the word line driving signals are generated in the divided cell arrays, a bit line sense signal is generated a predetermined delay time after all the word line driving signals have been generated, in order to drive all the sense amplifiers simultaneously, so that data can be definitely read from the memory cells to the bit lines.

Abstract: In a memory device according to the present invention, an address for writing input data into a memory (306) is designated by a first address counter (303) which operates in response to a first clock, an address for reading written data from the memory (306) is designated by a second address counter which operates in response to a second clock, and a phase difference between the outputs of the individual address counter means (303, 313) is detected by a phase comparing section (307). A timing generating section (114-116) delays a signal acquired from the first or second clock to generate three or more timings, a time difference between any two of the timings being a any non-integer multiple of the first or second clock cycle. Further, a phase comparison discriminating section (120-122, 126) latches the output of the phase comparing section (307) at three or more timings, and outputs a signal for controlling a second address counter section (313) by majority decision on the latching result.

Abstract: A method is provided for flash writing to multiple cells of a memory array. Initially, a first set of word lines, each of which controls connection of a memory cell of a first set of memory cells to a first bit line of a bit line pair, is turned on. The voltage between the two bit lines of the bit line pair is then equalized so that the charge on the first bit line of the bit line pair is higher than the charge on the second bit line of the bit line pair. Next, a sense amplifier attached to the bit line pair is turned on to sense a difference in charge between the bit line pair and to charge the first set of memory cells. Then a second set of word lines, each of which controls connection of a memory cell of a second set of memory cells to the second bit line is turned on. Finally, the word lines previously turned on are shut off and then the sense amplifier is shut off.

Abstract: A fast memory bit cell suitable for implementation in VLSI techniques permitting a high cell density. The cell includes a cell circuit in which a logical bit value is storable, a first connection permanently tied to a supply voltage, a second, third and fourth connection, each able to assume a different control state. Each combination of control states on the second, third and fourth connection sets the memory bit cell in an individual among a set of functional states.

Abstract: A method of repairing overerased cells in a flash memory array including a column having a first cell and a second cell is described. Repair begins by determining whether a first cell is overerased and applying a programming pulse if so. Next, the second cell is examined to determine whether it is overerased. A programming pulse is applied to the second cell if it is overerased. Afterward, if either of the cells was overerased then the repair pulse voltage level is incremented. These steps are repeated until none of the cells on the column is identified as overerased.

Abstract: Based on address data of memory cells inputted in a first operating cycle of a host system, data is read from a selected memory cell and outputted from a sense amplifier. At this time, a switch is turned on to allow the output data of the sense amplifiers to be stored in a read storage device. The host system does not accept the data stored in the read storage device and outputted from an A-port data input/output terminal then. Next, the switch is turned off based on address data of the read storage device inputted from the host system in a second operating cycle thereof. In the second operating cycle, the host system accepts the data stored in the read storage device and outputted from the A-port data input/output terminal. In this way, data reading from a memory cell is executed in two operating cycles, and a delay due to the memory cell array and one due to a wiring capacitance of signal lines between the semiconductor memory device and host system are distributed to the respective operating cycles.

Abstract: A memory security device within a chip which employs a power source coupled to the memory. The power source produces a signal having a level sufficient to erase or destroy the memory when the chip is exposed to acid. The power source includes an electrolytic cell for producing a direct voltage output, and an electrolytic signal amplification circuit coupled between the electrolytic cell and the memory.

Abstract: The present invention is directed to semiconductor memories which can operate at faster speeds with reduced power dissipation. In a preferred embodiment, load devices of a memory array, such as a SRAM, are automatically turned off during a write operation in response to detected bit line activity. Accordingly, considerable power is saved while minimizing memory architecture and the potential for power surges during a write enable.

Abstract: There is disclosed a DRAM having a 16 bit configuration which can be used for either a 2CAS/1WE type or a 1CAS/2WE type. The type of DRAM to be used is determined by whether there is a connection through a gold wire between a predetermined bonding pad and a lead for ground potential. Depending on the state of the connection of the bounding pad, conversion buffer converts externally applied control clock signals to internal control clock signals for either the 2CAS/1WE or the 1CAS/2WE. A clock generator not shown is operated in response to the converted internal control clock signals. The type of DRAM to be used is determined by whether there is a connection through a gold wire which is provided at the final step in a manufacturing process, so that the manufacturing processes are unified and therefore the type of DRAM to be used can be altered quickly depending on a drastically changing demand. In addition, efficiency in manufacturing a DRAM is enhanced.

Abstract: A DRAM includes a test mode controller generating a test mode designating signal designating a test mode at a fall of an external control signal RAS when the logical levels of external control signals CAS and WE are low, and a power-on reset circuit responsive to a power supply for generating a reset pulse for resetting main circuits for data reading and data writing. Each of the external control signals CAS and WE are supplied to the test mode controller and the main circuits through a buffer circuit. A first buffer circuit for supplying the external control signal RAS to the test mode controller is provided separately from a second buffer circuit for supplying the external control signal RAS to the main circuits. The second buffer circuit receives the output of the power-on reset circuit and the external control signal RAS to buffer the control signal RAS only when no reset pulse is generated.

Abstract: A non-volatile memory is described. The memory includes a memory array that includes a main block and a boot block. The memory also includes a control input for receiving a control signal. The control signal can be in a first voltage state, a second voltage state, and a third voltage state. Circuitry means is coupled to receive the control signal at the control input for (1) allowing the boot block to be updated when the control signal is in the first state and for (2) generating a power off signal to switch the memory into a substantially powered off state when the control signal is in the third voltage state. A method of controlling a non-volatile memory is also described.