Abstract: A flash memory system for an A/V player, utilizing a two-level round-robin write scheme upon N flash memory planes, enabling the A/V player to be loaded with data at a data throughput essentially N times the write throughput of one of the flash memory planes. The flash chips' memory cores and data registers, and the memory system's write buffers, can be kept fully utilized during data writing.
Abstract: A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.
Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and the number of times of writing is not limited. The semiconductor device is formed using a wide gap semiconductor and includes a potential change circuit which selectively applies a potential either equal to or different from a potential of a bit line to a source line. Thus, power consumption of the semiconductor device can be sufficiently reduced.
February 7, 2011
Date of Patent:
November 27, 2012
Semiconductor Energy Laboratory Co., Ltd.
Abstract: Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and columns, each dynamic random access memory cell including one or more memory transistors. The one or more memory transistors of the apparatus for reducing a voltage swing may comprise: a first region coupled to a source line, a second region coupled to a bit line, a first body region disposed between the first region and the second region, wherein the first body region may be electrically floating, and a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region.
Abstract: A current detection circuit that can normally perform a current detection operation to detect a current in a memory cell of a memory device even if an applied power supply voltage is a low voltage, includes a current detection means which comprises first and second MOS transistors of a same channel type and third to sixth MOS transistors of a channel type different from the channel type of the first and second MOS transistors, and a MOS gate control means which supplies, to a control electrode of each of the first and second MOS transistors, a voltage which is obtained by subtracting an absolute value of a threshold voltage of each of the first and second MOS transistors from the power supply voltage when the power supply voltage is equal to or lower than the absolute value of the threshold voltage.
Abstract: A flash memory device comprises alternately arranged odd and even memory cells. The odd and even memory cells are connected to corresponding odd and even bitlines, which are connected to corresponding odd and even page buffers. In a read operation of the flash memory device, data is sensed at two different times via the odd and even bitlines. In certain embodiments, data is read from the odd page buffers while data is being sensed via the even bit lines, or vice versa.
Abstract: A semiconductor memory device comprises a plurality of first row lines arranged in parallel; a plurality of column lines intersecting the first row lines; a plurality of storage elements arranged at intersections of the first row lines and the column lines; a plurality of second row lines arranged in parallel with the first row lines, from positions opposite to the first row lines via the column lines to a certain portion of the column line, and capacitively coupled with the column lines; and a sense amplifier including a field effect transistor having a lower layer control electrode composed of the certain portion of the column line, and an upper layer control electrode composed of the second row line capacitively coupled in the upper layer with the certain portion of the column line.
Abstract: A semiconductor device according to the present invention performs, when a first word structure is designated, control such that input and output of data is performed from a first data input/output terminal and from a second data input/output terminal in response to a first strobe signal and a second strobe signal. The semiconductor device performs, when a second word structure is designated and when a first control signal is supplied, control such that input and output of data is performed from the first data input/output terminal in response to the first strobe signal. The semiconductor device performs, when the second word structure is designated and when a second control signal is supplied, control such that input and output of data is performed from the second data input/output terminal in response to the second strobe signal.
Abstract: A semiconductor memory device comprises memory cells which includes a selection transistor and a memory transistor; selection gate lines coupled to a gate of the selection transistor; control gate lines coupled to the control gate of the memory transistor; source lines coupled to a source of the memory transistor; bit lines coupled to the selection transistor; a selection gate line driver circuit; a control gate line driver circuit; and a source line driver circuit, wherein the selection gate line driver circuit comprises a first transistor including a first gate insulation film and drives the selection gate line with a first driving voltage, and the control gate line driver circuit and the source line driver circuit comprises a second transistor including second gate insulation films and drives the control gate line and the source line with a boost voltage higher than the first driving voltage.
Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film and a memory cell transistor. The transistor is provided for each of storage regions configured to store charge in the film.
Abstract: A nonvolatile memory includes memory blocks each including a data storage area for storing user data and a discrimination area that is provided so as to correspond to the each data storage area on a one-to-one basis and stores discriminative data indicating a writing state of data to the data storage area. The nonvolatile memory further includes a control circuit which determines the data storage area that will be a storage destination of the user data based on a relative difference relation among the discriminative data of the respective memory blocks, and changes the discriminative data of the discrimination area corresponding to the data storage area in which the user data was written to a value different from that before the writing.
Abstract: According to an embodiment, there are provided a non-volatile semiconductor memory device includes: a memory cell array; a control circuit performing a series of operations to each memory cell and determining, as a defective memory cell, a memory cell whose data retention property does not satisfy a criteria, the series of operations including an operation applying a first bias to the memory cell in a forward direction, and including an operation thereafter applying a second bias to the memory cell in a reverse direction; a storage unit storing an address of the defective memory cell; and an address control unit performing a control to avoid storing data in the defective memory cell whose address is stored in the storage unit.
Abstract: A resistance change memory device includes: memory cells each having a current path in which a storage element, whose resistance changes according to the voltage applied, and an access transistor are connected in series; first wirings each connected to one end of the current path; second wirings each connected to the other end of the current path; a well which is a semiconductor region in which the access transistors are formed; and a drive circuit.
Abstract: A non-volatile semiconductor storage device according to an embodiment includes: a memory cell array including an array of electrically rewritable memory cells and configured to be able to store N bits of data (where N is a natural number not less than 2) in one memory cell; and a controller operative to control read, write and erase operations of the memory cell array. The memory cell array includes a first region having a first memory cell operative to retain N bits of data, and a second region having a second memory cell operative to retain M bits of data (where M is a natural number less than N). A data structure of address data received by the controller when accessing the first memory cell is the same as a data structure of address data received from the outside when accessing the second memory cell.
Abstract: According to one embodiment, a semiconductor storage device includes a first cell, a second cell, a bit line, a first buffer, a second buffer, and a controller. The bit line transfers the data to the first cell and the second cell. The first buffer holds write data to the first cell and the second cell. The second buffer holds read data from the first cell. The controller controls first writing and rewriting executed for the first cell and second writing executed for the second cell. The write data in the first buffer is updated each time a second write signal is given. The controller executes the first writing based on the write data held by the first buffer. The controller performs the second writing based on the write data updated in the first buffer. The controller executes the rewriting based on the read data held by the second buffer.
Abstract: According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block.
Abstract: A nonvolatile semiconductor memory device and a nonvolatile memory system having a unit which suppresses erroneous reading of a nonvolatile semiconductor memory device of a multi-level memory system are provided. In the nonvolatile semiconductor memory device and the nonvolatile memory system of the multi-level memory system, a first verify voltage is used when data is written before a packaging process, and the verify voltage is switched to a second verify voltage lower than the first verify voltage when data is written after the packaging process.
Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.
Abstract: A semiconductor device and a method for testing the same are disclosed, relating to a technology for simultaneously screening an off-leakage-current fail caused by a passing gate effect and a neighbor gate effect. The semiconductor device includes a memory cell configured to read and write data; a sense amplifier configured to sense and amplify cell data received from the memory cell through a pair of bit lines; a bit line precharge unit configured to equalize the pair of bit lines to a level of a ground voltage in response to a bit line equalization signal; a precharge voltage generator configured to provide the ground voltage to the bit line precharge unit during a test mode; and a test controller configured to, during the test mode, maintain an activation state of the bit line equalization signal during a test mode period, and control the sense amplifier to be deactivated.
Abstract: According to one embodiment, a nonvolatile memory device includes a memory unit and a control unit. The memory unit includes first and second interconnects, and a memory cell. The second interconnect is non-parallel to the first interconnect. The memory cell includes a resistance change layer provided at an intersection between the first and second interconnects. The control unit is connected to the first and second interconnects to supply voltage and current to the resistance change layer. The control unit increases an upper limit of a current supplied to the first interconnect based on a change of a potential of the first interconnect when applying a set operation voltage to the first interconnect in a set operation of changing the resistance change layer from a first state with a first resistance value to a second state with a second resistance value being less than the first resistance value.