Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for controlling refresh operations. Responsive to a refresh command, or one or more pumps generated responsive to the refresh command, different banks of a memory array may perform different types of refresh operations for a pump. In some examples, the type of refresh operation performed by a bank may vary from pump to pump of a refresh operation.

Abstract: A memory device according to the present technology includes a memory cell array configured to include planes having a plurality of memory cells, a page buffer connected to at least one memory cell among the memory cells through a bit line and configured to perform a sensing operation of reading data stored in the at least one memory cell connected to the bit line, a common reference voltage generator configured to generate a common reference voltage, a plurality of merged buffers configured to generate a reference signal using the common reference voltage, and control logic configured to control an operation of the common reference voltage generator and the merged buffers so that page buffer control signals generated based on the reference signal are supplied to the page buffer.

Abstract: Methods, systems, and devices for dynamic read voltage techniques are described. In some examples, a memory device may include one or more partitions made up of multiple disjoint subsets of memory arrays. The memory device may receive a read command to read the one or more partitions and enter a drift determination phase. During the drift determination phase, the memory device may concurrently apply a respective voltage of a set of voltages to each disjoint subset and determine a quantity of memory cells in each disjoint subset that have a threshold voltage below the applied voltage. Based on a comparison between the determined quantity of memory cells and a predetermined quantity of memory cells, the memory device may select a voltage from the set of voltages and utilize the selected voltage to read the one or more partitions.

Abstract: An internal voltage generation device includes: a voltage detection circuit generating a first detection signal by comparing a first voltage with a target voltage; a voltage difference detection circuit enabled in response to an operation enable signal, generating a second detection signal by comparing a voltage difference between the first voltage and a second voltage with a target gap voltage; a control circuit generating a first up/down code and the operation enable signal according to the first detection signal, and generating a second up/down code according to the second detection signal; a first voltage generation circuit generating the first voltage by down-converting a supply voltage, and adjusting a level of the first voltage according to the first up/down code; and a second voltage generation circuit generating the second voltage by boosting up the supply voltage, and adjusting a level of the second voltage according to the second up/down code.

Abstract: An amplifier with an input stage comprising: a first current mirror; a first input differential pair; a first current source; a second current source; a second input differential pair, wherein the first input differential pair and the second input differential pair receive a reference voltage; a second current mirror; and a voltage control transmission circuit. An extra current path in the first current mirror is formed and a current flowing through the extra current path flows through the second current mirror to a ground when the reference voltage is higher than a first predetermined value. Also, an extra current path in the second current mirror is formed and a current flowing through the extra current path in the second current mirror flows to the first current mirror when the reference voltage is lower than a second predetermined value.

Abstract: A multi-layer vector-matrix multiplication (VMM) apparatus is provided. The multi-layer VMM apparatus includes a three-dimensional (3D) NAND flash structure having multiple transistor array layers each includes a number of transistors configured to store a respective weight matrix and a number of word lines configured to receive respective selection voltages corresponding to a respective input vector. Accordingly, each of the transistor array layers can perform a respective VMM operation by multiplying the respective selection voltages with the respective weight matrix. Thus, by providing the respective selection voltages to each of the multiple transistor array layers in a sequential order, it may be possible to carry out a multi-layer VMM operation in the 3D NAND flash structure with reduced footprint, thus making it possible to support a deep neural network (DNN) via such advanced techniques as in-memory computing.

Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Abstract: Methods and apparatus are disclosed for managing the storage of static and dynamic neural network data within a non-volatile memory (NVM) die for use with deep neural networks (DNN). Some aspects relate to separate trim sets for separately configuring a static data NVM array for static input data and a dynamic data NVM array for dynamic synaptic weight data. For example, the static data NVM array may be configured via one trim set for data retention, whereas the dynamic data NVM array may be configured via another trim set for write performance. The trim sets may specify different configurations for error correction coding, write verification, and read threshold calibration, as well as different read/write voltage thresholds. In some examples, neural network regularization is provided within a DNN by setting trim parameters to encourage bit flips to avoid overfitting. Some examples relate to managing non-DNN data, such as stochastic gradient data.

Abstract: A volatile memory device includes: a first sense amplifier connected to a first memory cell through a first bit line, and configured to sense 2-bit data stored in the first memory cell; a second sense amplifier connected to a second memory cell through a second bit line, and configured to sense 2-bit data stored in the second memory cell, the second bit line having a length greater than a length of the first bit line; and a driving voltage supply circuit configured to supply a first driving voltage to the first sense amplifier, and supply a second driving voltage to the second sense amplifier, the second driving voltage having a voltage level different from a voltage level of the first driving voltage.

Abstract: Apparatuses and methods for calculating targeted refresh addresses may include circuitry that may be used to calculate victim row addresses having a variety of spatial relationships to an aggressor row. The spatial relationship of the victim row addresses calculated by the circuitry may be based, at least in part, on states of control signals provided to the circuitry. That is, the circuitry may be used to calculate the different victim row addresses by changing the states of the control signals.

Abstract: Apparatuses, mufti-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: Nonvolatile memory device includes memory cell region including first metal pad, peripheral circuit region including second metal pad, memory cell array, input current generator, operation cell array and analog-to-digital converter. Peripheral circuit region is vertically connected by first and second metal pads. Memory cell array in memory cell region includes NAND strings storing multiplicand data, wherein first ends of NAND strings are connected to bitlines and second ends of NAND strings output multiplication bits corresponding to bitwise multiplication of multiplicand data stored in NAND strings and multiplier data loaded on bitlines. Input current generator generates input currents. Operation cell array in memory cell region includes switching transistors. Gate electrodes of switching transistors are connected to second ends of NAND strings. Switching transistors selectively sum input currents based on multiplication bits to provide output currents.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device compares a received signal with an original signal to generate a driving force control signal. The first semiconductor device also drives the original signal using a driving force in accordance with the driving force control signal to output an external transmission signal. The second semiconductor device receives the external transmission signal to generate a positive signal and a negative signal. The second semiconductor device also generates a restoration signal in response to the positive signal and the negative signal. The second semiconductor device additionally outputs the restoration signal as the external transmission signal to the first semiconductor device.

Abstract: Disclosed herein are mechanisms and methods for reducing power consumed by various DRAM technologies (e.g., high-capacity DRAM and/or 3D DRAM) which may impact battery life of the platform. These mechanisms and methods may opportunistically reduce the power consumed by DRAM by inhibiting periodic refresh commands to memory ranks that are not in-use. Since these mechanisms and methods may be based on enhancements to memory controllers, they may accordingly be operating system (OS) agnostic.

Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

Abstract: A system includes a charge pump to charge wordlines of a memory array, a pump regulator coupled including a level detector, and dynamic clock logic coupled between the level detector and an oscillator. The logic provides clock signals to the charge pump and is to perform operations including: detecting that the charge pump has entered a recovery period; causing the oscillator to output, to the charge pump during a first time period of the recovery period, a first clock signal comprising a lower frequency than output during a time period preceding the recovery period; detecting that a voltage level from the level detector satisfies a trip point criterion; and causing the oscillator to output, to the charge pump during a second time period of the recovery period and responsive to the detecting, a second clock signal comprising a higher frequency than output during the time period preceding the recovery period.

Abstract: A memory device includes a memory group and a control circuit. The memory group includes several memory banks. The control circuit is coupled to the memory group. The control circuit includes a tri-state logic enable circuit and an address decoding circuit. The tri-state logic enable circuit is configured to temporarily store several temporarily stored address signals, to output the several temporarily stored address signals according to a synchronization signal, to decode the several temporarily stored address signals to generate an enable signal, and to transmit the enable signal to one of the several memory banks. The address decoding circuit is configured to decode the several temporarily stored address signals to drive the one of the several memory banks.

Abstract: Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.