Patents Examined by Aracelis Ruiz
  • Patent number: 11841793
    Abstract: Computing devices, methods, and systems for switch-based free memory tracking in data center environments are disclosed. An exemplary switch integrated circuit (IC), which is used in a switched fabric or a network, can include a processing device and a tracking structure that is distributed with at least a second switch IC. The tracking structure tracks free memory units that are accessible in a first set of nodes by the second switch IC. The processing device receives a request for a number of free memory units. The processing device forwards the request to a node in the first set of nodes that has at least the number of free memory units or forwards the request to the second switch IC that has at least the number of free memory units or responds to the request with a response that indicates that the request could not be fulfilled.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: December 12, 2023
    Assignee: Rambus Inc.
    Inventors: Steven C. Woo, Christopher Haywood, Evan Lawrence Erickson
  • Patent number: 11842049
    Abstract: Technologies are provided for dynamically changing a size of a cache region of a storage device. A storage device controller writes data to the cache region of the storage device using a particular storage format. The storage device controller then migrates the cached data to a storage region of the device, where the data is written using a different storage format. A dynamic cache manager monitors input and output activity for the storage device and dynamically adjusts a size of the cache region to adapt to changes in the input and/or output activity. The dynamic cache manager can also adjust a size of the storage region. The storage device controller can automatically detect that the storage device has dynamic cache support and configure the storage device by creating the cache region and the storage region on the device.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: December 12, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Munif M. Farhan, Phyllis Ng, Darin Lee Frink, Nafea Bshara
  • Patent number: 11841802
    Abstract: A microprocessor prevents same address load-load ordering violations. Each load queue entry holds a load physical memory line address (PMLA) and an indication of whether a load instruction has completed execution. The microprocessor fills a line specified by a fill PMLA into a cache entry and snoops the load queue with the fill PMLA, either before the fill or in an atomic manner with the fill with respect to ability of the filled entry to be hit upon by any load instruction, to determine whether the fill PMLA matches load PMLAs in load queue entries associated with load instructions that have completed execution and there are other load instructions in the load queue that have not completed execution. The microprocessor, if the condition is true, flushes at least the other load instructions in the load queue that have not completed execution.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: December 12, 2023
    Assignee: Ventana Micro Systems Inc.
    Inventors: John G. Favor, Srivatsan Srinivasan
  • Patent number: 11836086
    Abstract: Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting, in each cache way of a group of cache ways, a number of dirty cache lines having dirty bits indicating the cache line has been modified; selecting, from the group, at least one cache way for collapse, based on its corresponding number of dirty cache lines; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: December 5, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Hithesh Hassan Lepaksha, Sharath Kumar Nagilla, Darshan Kumar Nandanwar, Nirav Narendra Desai, Venkata Biswanath Devarasetty
  • Patent number: 11836080
    Abstract: A L2 cache is set associative, has N ways, and is inclusive of a virtual L1 cache such that when the virtual address misses in the L1: a portion of the virtual address is translated into a physical memory line address (PMLA), the PMLA is allocated into an L2 entry, and a physical address proxy (PAP) for the PMLA is allocated into an L1 entry. The PAP for the PMLA includes a set and a way that uniquely identify the L2 entry. The L2 receives a physical memory line address for allocation, uses a set index portion of the PMLA, and for each L2 way, forms a PAP corresponding to the way. The L1, for each PAP, generates a corresponding indicator of whether the PAP is L1 resident. The L2 selects, for replacement, a way whose indicator indicates the PAP is not resident in the L1.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: December 5, 2023
    Assignee: Ventana Micro Systems Inc.
    Inventors: John G. Favor, Srivatsan Srinivasan, Robert Haskell Utley
  • Patent number: 11829647
    Abstract: A storage system has a memory with a multi-level cell (MLC) block that can store multiple bits per cell or can be constrained to store only one bit per cell. Using the MLC block to store only one bit per cell can increase the performance of the storage system but can also reduce endurance of the MLC block. The storage system can monitor a command queue to determine the performance needed. With that information, the storage system can determine whether it is worth making the tradeoff of increasing performance at the cost of endurance.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: November 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kalpit Bordia, Disha Gundecha, Raviraj Raju
  • Patent number: 11822480
    Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: November 21, 2023
    Assignee: Apple Inc.
    Inventors: Tyler J. Huberty, Vivek Venkatraman, Sandeep Gupta, Eric J. Furbish, Srinivasa Rangan Sridharan, Stephan G. Meier
  • Patent number: 11822485
    Abstract: Methods, systems, and computer-readable storage media for maintaining and utilizing a unified cache memory. The method first identifies a unified cache memory associated with an application and populates it with data for access during application execution. The unified cache memory is associated with coupled lookup elements, which include multiple keys and multiple values coupled together. The coupled lookup elements are available to the application for access to all possible views of the data.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: November 21, 2023
    Assignee: Appian Corporation
    Inventor: Brian Sullivan
  • Patent number: 11816039
    Abstract: Multi-mode protected memory in accordance with the present description includes a permanent mode and a transient mode of operation. In one embodiment of the permanent mode, an authentication key is programmable once and a write counter is not decrementable or resettable. In one embodiment of the transient mode, an authentication key may be programmed many times and a write counter may be reset many times. Other features and advantages may be realized, depending upon the particular application.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventors: Adrian Pearson, Bing Zhu, Elena Agranovsky, Tomas Winkler, Yang Huang
  • Patent number: 11809325
    Abstract: In addition to caching I/O operations at a host, at least some data management can migrate to the host. With host side caching, data sharing or deduplication can be implemented with the cached writes before those writes are supplied to front end storage elements. When a host cache flush to distributed storage trigger is detected, the host deduplicates the cached writes. The host aggregates data based on the deduplication into a “change set file” (i.e., a file that includes the aggregation of unique data from the cached writes). The host supplies the change set file to the distributed storage system. The host then sends commands to the distributed storage system. Each of the commands identifies a part of the change set file to be used for a target of the cached writes.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: November 7, 2023
    Assignee: NetApp, Inc.
    Inventors: Girish Kumar Bk, Gaurav Makkar
  • Patent number: 11809712
    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: November 7, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern
  • Patent number: 11809332
    Abstract: An apparatus includes circuitry couplable to a host system and a memory device. The circuitry is configured to determine whether a page table maintained on the circuitry includes a physical address of the memory device corresponding to a virtual address associated with a TLB fill request from the host system. Responsive to determining that the page table includes the physical address, the circuitry provides signaling indicative of a completion to the TLB fill request to the host system, prefetch a page of data at the physical address from the memory device using the physical address from the page table, and provide signaling indicative of the page of data to the host system.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Paul Rosenfeld, Robert M. Walker
  • Patent number: 11803480
    Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: October 31, 2023
    Assignee: Apple Inc.
    Inventors: Michael R. Seningen, Ben D. Jarrett, Edward M. McCombs, Greg M. Hess
  • Patent number: 11797451
    Abstract: The disclosure is directed to techniques for dynamically managing memory in mixed mode cache and shared memory systems. For example, a system on a chip (SoC) comprises: a plurality of memories, including a first memory and a second memory, where each of the memories includes one or more cache lines; a first subsystem comprising a first compute element and the first memory; a second subsystem comprising a second compute element and the second memory; and a memory control unit of the SoC comprising processing circuitry and configured to: configure a shared memory with one or more cache lines of at least one of the plurality of memories; and flush, based on one or more tag control bits for the one or more cache lines of the shared memory, data from the shared memory to a backend storage separate from the SoC.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: October 24, 2023
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Sridhar Gurumurthy Isukapalli Sharma, Valerio Catalano
  • Patent number: 11797457
    Abstract: An electronic apparatus according an embodiment includes a first memory, a second memory, a gate device, and one or more hardware processors. The first memory stores information. The second memory stores state information indicating whether or not update on the information of the first memory is allowed. The gate device is provided on a bus and controls whether or not to permit access to the second memory based on a control instruction. In a predetermined mode, the one or more hardware processors output, to the gate device, a control instruction to permit access to the second memory, set the state information of the second memory to indicate an updatable state, and update the information of the first memory.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: October 24, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kento Shiratori, Hiroaki Tanaka
  • Patent number: 11789859
    Abstract: To generate sequential addresses when multiple integrated circuit (IC) devices are accessing the same memory, an address token is sent along the IC devices communicatively coupled in a ring topology. The address token is first transferred along the ring topology during a memory reservation phase in which each IC device can set a corresponding memory request bit to indicate that the IC device has data to write to the memory. The modified address token is then transferred along the ring topology again during a memory access phase. During the memory access phase, each IC device that has data to write can perform a memory write operation using a sequential address determined from the contents of the address token.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: October 17, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Kun Xu, Suresh Hariharan
  • Patent number: 11789661
    Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: October 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Angelo Della Monica, Eric Kwok Fung Yuen, Pasquale Cimmino, Massimo Iaculo, Francesco Falanga
  • Patent number: 11789871
    Abstract: A microprocessor prevents same address load-load ordering violations. Each load queue entry holds a load physical memory line address (PMLA) and an indication of whether a load instruction has completed execution. The microprocessor fills a line specified by a fill PMLA into a cache entry and snoops the load queue with the fill PMLA, either before the fill or in an atomic manner with the fill with respect to ability of the filled entry to be hit upon by any load instruction, to determine whether the fill PMLA matches load PMLAs in load queue entries associated with load instructions that have completed execution and there are other load instructions in the load queue that have not completed execution. The microprocessor, if the condition is true, flushes at least the other load instructions in the load queue that have not completed execution.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: October 17, 2023
    Assignee: Ventana Micro Systems Inc.
    Inventors: John G. Favor, Srivatsan Srinivasan
  • Patent number: 11775046
    Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: October 3, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Oluleye Olorode, Mehrdad Nourani
  • Patent number: 11762773
    Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: September 19, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Daniel Marcovitch, Gil Bloch, Richard Graham, Ariel Shahar, Roee Moyal, Igor Voks