Abstract: A data processing system has a bus meter, a memory capable of transferring operands requested by the bus master, and a cache for temporarily storing a selected number of the most recently transferred operands. If the memory provides an operand or a portion thereof which is insufficient in size or alignment to fill a complete entry in a line in the cache, the bus master automatically transfers additional operands adjacent in the memory to the requested operand sufficient to fill that entry.

Abstract: A printer has a printing mechanism for printing on printing paper in accordance with data stored in a buffer memory which is divided into a non-overwrite memory region and an overwrite memory region. The data entered from an external device is first stored in the non-overwrite memory region of the buffer memory. If the data in the non-overwrite memory region exceeds the storage capacity during printing, the excess data is stored in the overwrite memory region. When the data stored in the overwrite memory region exceeds the storage capacity, the printer overwrites subsequent data entered from the external device onto the previous data stored therein. Moreover, during reprinting, the data in the non-overwrite memory region of the buffer memory is read to activate the printing mechanism.

Abstract: A data processing system having a main memory, includes instruction prefetch queue for fetching instructions from the main memory; processing unit for interpreting the instructions from the prefetch queue; and selection unit for selecting a predetermined set of control signals from a plurality of control signals input and output for the processing unit to fetch the instructions from the instruction prefetch queue.

Abstract: A system for adjusting a performance of an information processing apparatus which provides a unit indicating a target performance value, a unit generating a corresponding performance control pulse in accordance with the target performance value, and an execution control unit which alternately sets an execution period and an execution inhibiting period in accordance with the performance control pulse. The unit which generates the performance control pulse makes a ratio of a pulse width and a pulse period of the performance control pulse coincide with the target performance value.

Abstract: A computer program measures the execution of machine code instructions in an executing program. A copy of the measured program is made and selected machine instructions are replaced by interrupt-causing breakpoint instructions. As each breakpoint instruction is executed, the breakpoint is replaced by the actual instruction, and a bit map is updated to indicate execution of the measured instruction. Execution resumes with the actual instruction.

Abstract: A data processing apparatus includes a self-running type shift register and this shift register includes a plurality of latch registers arranged in a cascade fashion. The latch register latches a data packet on a word basis. In each latch register, a coincidence element is disposed in association therewith and these coincidence elements allow transfer of data from a post-stage latch register provided that a pre-stage latch register is vacant. A data processing element is installed between two latch registers and the data processing element processes operand data from either or both of the two latch register in response to the kind of processing shown by an operation code comprised in the preceding word. The result of processing is transferred to the pre-stage latch register when the pre-stage latch register is placed in the vacant state under control of the coincidence element.

Abstract: A microprogram control unit is provided for processing conditional branch micro-instructions stored in a micro-instruction memory to control the function of an information processing apparatus. The unit includes a microprogram counter coupled to the micro-instruction memory and contains an address for accessing the micro-instruction stored in the memory. A circuit is provided for registering the micro-instruction received from the micro-instruction memory and having an address field coupled to the microprogram counter and a condition field for designating a condition to be judged. A detecting circuit is coupled to the registering circuits to receive the micro-instruction therefrom and for detecting the conditional branch micro-instruction. Further, there is provided a circuit for generating status signals representing respectively a plurality of the status of the information processing apparatus and selectively outputting anyone of the status signals.

Abstract: A word processing apparatus is capable of logotype printing with a standard dot matrix pattern, and is controlled as to provide zero spacing between characters at logotype printing.

Abstract: A data processing circuit that performs either a merge or Boolean logic operation on data within a single clock cycle in response to an instruction. The circuit includes a control circuit for receiving an instruction during a clock cycle and providing a plurality of control signals in response to the instruction. Data selector circuitry is included for providing a plurality of data words in response to the control signals from the control circuit. Additionally, a rotator is connected to at least one data selector for rotating at least one of the data words in response to a control signal from the control circuit. Logic circuitry is provided for logically combining bits form the rotator and the data selector circuitry in response to control signals from the control circuit for providing data output within the single clock cycle.

Abstract: A pair of bus controllers are connected to a common bus and operated by high speed video digitizing timing signals for passing, in real time, the digitized data from incoming digitizing circuitry to output circuitry which converts the digitized data into video signals. A memory is connected by another bus to a computer, and a bus interface or selective dual ports of the memory selectively connect the memory to the common digital data bus so that digitized signals are written to and read from the memory in real time in accordance with the high speed timing signals and corresponding address signals.

Abstract: An editing system for use in a word processor includes a letter code producer for sequentially producing letter codes, a document memory having a plurality of memory elements aligned in vertical and horizontal directions with each memory element capable of storing one letter code, and an arrangement for setting vertical and horizontal boundaries within the document memory to divide the document memory into a plurality of columns or blocks, each column or block, having a plurality of lines, and different priorities being assigned to the columns or block. A column buffer is provided for storing line addresses from top to bottom in each of the columns or blocks and in the order of columns or blocks having a higher priority, and an address data producer is provided for sequentially producing address data of the memory elements in each line and in the order of lines as stored in the column buffer.

Abstract: A dynamic random-access memory (DRAM) has a first refresh circuit for producing memory refreshes during power-up, and a second refresh circuit for producing memory refreshes during power-down. The power-down refresh circuit is powered by a battery, and has a lower power consumption than the power-up circuit. During transition from power-down to power-up, the frequency of refreshing is doubled for a short period, so as to build up a surplus of refreshes. This allows refreshing to stop while the first or power-up refresh circuit is brought back into operation.

Abstract: A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain mutliple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration.

Abstract: According to a processing apparatus with a hierarchical structure, a machine instruction has a hierarchical structure of a task level operation code, a control structure level operation code, an arithmetic level operation code and a low order level operation code, and accordingly an operation object field has a hierarchical structure of task level data, control condition data, arithmetic object data and low order level data. In correspondence with the hierarchical structure of the instruction, the processing apparatus has a hierarchical structure of task level functional blocks, control structure level functional blocks, arithmetic level functional blocks and low order level functional blocks. The functional blocks respectively have instruction decoders which are operated with serial or parallel processing.

Abstract: A computer implemented logic simulation method, for inspecting logical operations of large scale logic circuits, computes a variation of an output of at least one latch in a clock synchronized logic circuit. The clock-synchronized logic circuit contains a combination logic circuit and a plurality of logic gates. Each of the logic gates have at least one input signal and several other inputs connected to clocking signal sources of different phases. The latch is activated by the rise or fall of the clock signals for holding the output from the combination logic circuit. The method thus implements sampling instants of the output for ascertaining the logical operations of the large scale circuits.

Abstract: A document manager controls the loading into memory from a mass storage means, such as a disk, a document file in disk file format. The loaded document file is stored in memory in document structure format for subsequent access thereto by a task, such as an application program. The loading of the document file into memory may be initiated by a task, either as a result of a user command or as a result of the operation of the task itself. In response to a request to load a document file, the document manager makes a request of a memory manager unit for an assigment of memory space to store the document file. After storage of the document file within the assigned memory space the document manager generates within the memory a document control block descriptive of various parameters associated with the loaded document. The document manager subsequently writes the location within memory of the generated document control block into an assigned location within the task requesting access to the document file.

Abstract: A personal computer/electronic typesetter interface includes an expansion board suitable for insertion into each of a plurality of personal computers functioning as page composition work stations, wherein one or more of the work stations is also connected for communication to an electronic typesetting machine. The expansion board includes logic for converting the data obtained in a preselected file from the coded format generated by the page composition work station to a second coded format recognized by the electronic typesetter to which the file is directed for output. The interface of the present invention also includes logic for continuously monitoring the status of the files in each of the queues, logic for interrupting the normal operation of the work station and displaying the first and second queues in response to a preselected command, and logic for allowing the operator to perform other file routing and queuing operations in response to other preselected commands.

Abstract: A semiconductor backing storage device is connected to a computer system accessible only in magnetic disc access mode for improvement in access time. In transferring information data between the computers and the semiconductor backing storage device, access control command signals peculiar to magnetic disc access mode are all disregarded and address data peculiar to magnetic disc access mode are converted into those necessary for semiconductor memory mode in writing or reading information data. To further decrease access time, one-word buffers are provided for a semiconductor backing storage controller and the backing storage device, so that the preceding data are transferred from the buffers while the current data are transferred to the buffers after necessary processing. The semiconductor backing storage memory is also usable for a multicomputer system by providing cross-call function for the semiconductor backing storage controller.

Abstract: A first-in-first out (FIFO) register 100 for storage of up to two-bytes of data is operable by two control units 10, 20 for simultaneous read and write operations with no wait states. The FIFO register 100 comprises a first register 101, a second register 102 and a controller U35. The first register 101 may be multplexed between the two control units 10, 20 for write operations by either unit. The second register 102 is in communication with the first register 101 and may be read by either control unit 10, 20. Data is transferred from the first register 101 to the second register 102 under the direction of the controller U35 such that data may be read by one control unit 10, 20 while data is being simultaneously written by the other control unit 10, 20.

Abstract: This invention relates to a loop transmission system which has a plurality of stations connected to a loop transmission path to transmit data among the stations. In the transmission frame to be sent out from the sending station, specific information is included for identifying each frame and this information is held in the sending station. When the transmission frame returns to the sending station after being transmitted through the loop transmission path, the specific information in the frame is received and compared with the information held in the station and, if they coincide, it is decided that the transmission frame has been correctly received by the intended receiving station.