Patents Examined by Arnold Kinkead
  • Patent number: 10211839
    Abstract: A bias-current-control circuit is provided. The bias-current-control circuit includes a transconductance circuit, a constant-current source, and a current-mirror circuit. The transconductance circuit is connected to a node and detects a voltage signal to generate a first current. The constant-current source is connected to the node and generates a tail current. The current-mirror circuit includes a reference current terminal and a bias current terminal, and the reference current terminal is coupled to the node. A second current which flows through the reference current terminal is determined by a current difference between the tail current and the first current. A bias current which flows through the bias current terminal is generated based on the second current. Furthermore, the second current and the bias current are in a predetermined ratio.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: February 19, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Yongqi Zhou
  • Patent number: 10205422
    Abstract: In accordance with an embodiment, a voltage controlled oscillator (VCO) includes a VCO core having a plurality of transistors and a varactor circuit that has a first end coupled to emitter terminals of the VCO core and a second end coupled to a tuning terminal. The varactor circuit includes a capacitance that increases with increasing voltage applied to the tuning terminal with respect to the emitter terminals of the VCO core.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: February 12, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Saverio Trotta
  • Patent number: 10205455
    Abstract: The disclosure provides a universal oscillator. The oscillator includes an amplifier array. The amplifier array includes one or more amplifiers. A control logic unit is coupled to the amplifier array and activates the one or more amplifiers. A self-clock generating circuit is coupled to the control logic unit and generates a fixed clock. A counter receives the fixed clock from the self-clock generating circuit and provides a controlled clock to the control logic unit.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: February 12, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Nagalinga Swamy Basayya Aremallapur
  • Patent number: 10200036
    Abstract: Provided is a Precision Voltage Reference (PVR). In one example, the PVR includes a resonator having an oscillation frequency, the resonator including a first proof-mass, a first forcer located adjacent a first side of the first proof-mass, and a second forcer located adjacent a second side of the first proof-mass. The PVR may include control circuitry configured to generate a reference voltage based on the oscillation frequency of the resonator, at least one converter configured to receive the reference voltage from the control circuitry, provide a first bias voltage to the first forcer based on the reference voltage, provide a second bias voltage to the second forcer based on the reference voltage, and periodically alter a polarity of the first and second bias voltages to drive the oscillation frequency to match a reference frequency, and an output configured to provide the reference voltage as a voltage reference signal.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: February 5, 2019
    Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.
    Inventors: Paul A. Ward, James S. Pringle, Marc S. Weinberg, Warner G. Harrison
  • Patent number: 10200045
    Abstract: A spread spectrum clock generator circuit includes a phase comparator; an oscillator to output an output clock signal; a phase selector to select one of phases equally dividing one cycle of the output clock signal, and to generate a phase shift clock signal having a rising edge in the selected phase; and a phase shift controller to control the phase selector. The phase shift controller generates a variable phase shift amount; determines the phase of the rising edge so that the cycle of the phase shift clock signal has a length changed from the cycle of the output clock signal by the variable phase shift amount added with a fixed phase shift amount; and changes a setting of an SS modulation profile if the selected phase exceeds an upper limit, falls below a lower limit, or is within the upper and lower limits.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: February 5, 2019
    Assignee: Ricoh Company, Ltd.
    Inventor: Senta Sekido
  • Patent number: 10191452
    Abstract: The present invention concerns a device (1) for an atomic clock. The device has a printed circuit board (20), a heating source, and microwave conductor. The printed circuit board (20) includes a conductive piece (10) for both interrogating and heating a gas in a cell of an atomic clock. The piece (10) has a gap (11), and is arranged for containing the cell (2), so as to directly touch the cell (2) in at least one point. The heating source (40, 60) generates heat, and is connected to the piece (10). The microwave conductor (12) is arranged to be connected to the piece (10) so as to send to the piece (10) a microwave signal for interrogating the atoms of the gas in the cell (2). This device performs more than one function (e.g. heating and interrogating) and simplify the manufacturing of the atomic clock.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: January 29, 2019
    Assignee: Orolia Switzerland SA
    Inventors: Pascal Rochat, Bernard Leuenberger
  • Patent number: 10187070
    Abstract: Electronic devices, local oscillator circuits, and methods for operating local oscillators are disclosed herein. In one embodiment, a local oscillator circuit includes a first transistor and a second transistor individually having a base, a collector, and an emitter and a transformer having a first transformer inductor magnetically coupled to a second transformer inductor. The first transformer inductor couples the collector of the first transistor to the base of the second transistor. The second transformer inductor couples the collector of the second transistor to the base of the first transistor.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: January 22, 2019
    Assignee: Washington State University
    Inventors: Suman P Sah, Deukhyoun Heo
  • Patent number: 10187073
    Abstract: An atomic oscillator includes a base, an atomic cell unit that is disposed on the base, a lid that constitutes an internal space accommodating the atomic cell unit together with the base, and a getter material that is disposed on the base with a gap with respect to the base in the internal space.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: January 22, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Yukihiro Hashi
  • Patent number: 10187074
    Abstract: A timing signal generation device includes a PLL circuit that synchronizes a first clock signal of an atomic oscillator with a reference timing signal of a GPS receiver, a PLL circuit that synchronizes a second clock signal of an oven-controlled crystal oscillator with the first clock signal, a first count reset unit that enables resetting of a count value of a divider in the PLL circuit when an operation of the PLL circuit is restarted, and a second count reset unit that enables resetting of a count value of a divider in the PLL circuit when the operation of the PLL circuit is restarted.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: January 22, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Shimada
  • Patent number: 10187066
    Abstract: An electronic device includes a drive section, a detection signal output section adapted to generate a first analog signal having a value varying in accordance with a physical quantity, and a control section adapted to generate a second analog signal controlled based on the first analog signal, and adapted to control a drive state of the drive section, at least the detection signal output section and the control section are provided to a substrate, and a first digital signal obtained by digitalizing the first analog signal and a second digital signal obtained by digitalizing the second analog signal can be output from the substrate.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: January 22, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Katsuyoshi Terasawa
  • Patent number: 10171090
    Abstract: An oscillator includes a vibrator element, a container in which the vibrator element is housed, at least one of a heating element and a cooling body configured to control the temperature on the inside of the container, an oscillation circuit electrically connected to the vibrator element, a D/A conversion circuit configured to control a frequency output by the oscillation circuit, and a reference-voltage generation circuit configured to supply a voltage to the D/A conversion circuit. The reference-voltage generation circuit is mounted on the inside of the container or on a substrate on which the container is mounted.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: January 1, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Masaaki Okubo
  • Patent number: 10171032
    Abstract: Apparatuses and methods for temperature independent oscillator circuits are disclosed herein. An example apparatus may include a pulse generator circuit configured to provide a periodic pulse based on the charging and discharging of a capacitor and further based on a reference voltage. The pulse generator circuit may include a capacitor coupled between a first reference voltage and a first node, wherein the capacitor is configured to be charged and discharged through the node in response to the periodic pulse, a resistor and a diode coupled in series between a second node and a second reference voltage, and a comparator coupled to the first and second nodes and configured to provide the periodic pulse based on voltages on the first and second nodes, wherein a period of the periodic pulse is based at least on the resistor and the a current.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jun Wu, Dong Pan
  • Patent number: 10170887
    Abstract: A surface emitting laser element includes a lower Bragg reflection mirror; an upper Bragg reflection mirror; and a resonator region formed between the lower Bragg reflection mirror and the upper Bragg reflection mirror, and including an active layer. A wavelength adjustment region is formed in the lower Bragg reflection mirror or the upper Bragg reflection mirror, and includes a second phase adjustment layer, a wavelength adjustment layer and a first phase adjustment layer, arranged in this order from a side where the resonator region is formed. An optical thickness of the wavelength adjustment region is approximately (2N+1)×?/4, and the wavelength adjustment layer is formed at a position where an optical distance from an end of the wavelength adjustment region on the side of the resonator region is approximately M×?/2, where ? is a wavelength of emitted light, M and N are positive integers, and M is N or less.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: January 1, 2019
    Assignee: RICOH COMPANY, LTD.
    Inventor: Ryoichiro Suzuki
  • Patent number: 10164573
    Abstract: A differential-logic logic circuit chained with another differential-logic circuit comprises a first logic cell composed of back-gate transistors, the first cell having a first input for receiving a first input signal and having an output for delivering a first output signal, and a second logic cell complementary to the first cell, composed of back-gate transistors, the second cell having as many inputs as the first cell, each input able to receive an input signal complementary to the respective input signal of the first cell, the second cell having an output for delivering a second output signal complementary to the first output signal of the first cell. The first output signal of the first cell is applied to the back gate of each transistor of the second cell, and the second output signal of the second cell is applied to the back gate of each transistor of the first cell.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: December 25, 2018
    Assignees: UNIVERSITE DE NICE, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Gilles Fernand Jacquemod, Emeric De Foucauld, Alexandre Benjamin Fonseca, Yves Leduc, Philippe Bernard Pierre Lorenzini
  • Patent number: 10164614
    Abstract: Embodiments of the present disclosure may provide a circuit comprising a tank circuit. The tank circuit may include an inductor having a pair of terminals, a first pair of transistors, and a first pair of capacitors. Each transistor may be coupled between a respective terminal of the inductor and a reference voltage along a source-to-drain path of the transistor. Each capacitor may be provided in a signal path between an inductor terminal coupled to a respective first transistor in the first pair and a gate of a second transistor in the first pair.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: December 25, 2018
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Xin Yang, Tianting Zhao, Baoxing Chen
  • Patent number: 10164574
    Abstract: A circuit for generating a plurality of oscillating signals with different phases includes a frequency divider, a first delay chain, a second delay chain and a calibration circuit. The frequency divider is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain is arranged for delaying the first frequency-divided input signal, and the second delay chain is arranged for delaying the second frequency-divided input signal. The calibration circuit is arranged for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; wherein output signals of a portion delay cells within the first delay chain and the second delay chain serve as the plurality of oscillating signals with different phases.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: December 25, 2018
    Assignee: MEDIATEK INC.
    Inventors: Yueh-Ting Lee, Yao-Chi Wang, Sheng-Che Tseng
  • Patent number: 10164316
    Abstract: A combining arrangement comprises a power combiner having at least four ports. A first match-dependent oscillator is connected to input power at a first frequency to a first input port of the power combiner. A second match-dependent oscillator is connected to input power at a second frequency to a second input port of the power combiner. A mismatch is connected to a third port of the power combiner. The power combiner is operative to combine power from the first and second oscillators and, when the first and second frequencies are different, to apply a fraction of the combined power to the mismatch. The mismatch reflects at least some of the fraction of the combined power to the first and second oscillators to phase and frequency lock their outputs. A fourth output port of the power combiner is connected to receive the combined power.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: December 25, 2018
    Assignee: TELEDYNE E2V (UK) LIMITED
    Inventors: Michael John Duffield, Craig Loch
  • Patent number: 10164571
    Abstract: An crystal resonator includes a first oscillating circuit that oscillates a crystal resonator at a first frequency, a first impedance adjusting circuit that adjusts an impedance of a first oscillating system including the crystal resonator and the first oscillating circuit, a second oscillating circuit that oscillates the crystal resonator at a second frequency that is different from the first frequency, a second impedance adjusting circuit that adjusts an impedance of a second oscillating system including the crystal resonator and the second oscillating circuit, and a controlling circuit that controls the first impedance adjusting circuit and the second impedance adjusting circuit.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: December 25, 2018
    Assignee: NIHON DEMPA KOGYO CO., LTD.
    Inventors: Takashi Nakaoka, Kazuo Akaike, Hiroshi Hoshigami, Kaoru Kobayashi
  • Patent number: 10153729
    Abstract: In some examples, a device includes a nano-scale oscillator that exhibits chaotic oscillation responsive to a control input to the nano-scale oscillator, where the control input including a tunable input parameter.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: December 11, 2018
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Suhas Kumar, John Paul Strachan, Gary Gibson, R. Stanley Williams
  • Patent number: 10153752
    Abstract: A relaxation oscillator circuit includes a current mirror configured to receive the input current from the and generate a plurality of starved currents, a Schmitt trigger configured to be current starved by a first starved current of the plurality of starved currents and a plurality of inverters configured to receive a Schmitt trigger output signal and generate an output clock signal, the inverters including a plurality of current starved inverters that are current starved by a second starved current of the plurality of starved currents, the plurality of current starved inverters receiving the Schmitt trigger output signal and generating a first inverter output signal, upon which an output clock signal is based. The relaxation includes a capacitor configured to charge or discharge in response to the output clock signal and a switching module configured to provide current from the current source based on the output clock signal.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: December 11, 2018
    Assignee: DISRUPTIVE TECHNOLOGIES RESEARCH AS
    Inventor: Bjørnar Hernes