Patents Examined by Arnold M. Kinkead
  • Patent number: 11901906
    Abstract: Presented herein are techniques for implementing a hybrid fractional-N sampling phase locked loop with accurate digital-to-time calibration. A method includes receiving, at a comparator, an output of a sampling phase detector of a phase locked loop, the output of the sampling phase detector of the phase locked loop also being supplied as a control source for a proportional control input of a voltage-controlled oscillator, supplying an output of the comparator as an input signal to a calibration loop of a digital-to-time converter, supplying an output of the digital-to-time converter to an input of the sampling phase detector, and supplying the output of the comparator as a control source for an integral control input of the voltage-controlled oscillator.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: February 13, 2024
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Abhishek Bhat, Romesh Kumar Nandwana, Pavan Kumar Hanumolu, Kadaba Lakshmikumar
  • Patent number: 11901864
    Abstract: A circuit includes an amplifier having an input and an output. A voltage comparator has an input and first and second outputs. The input of the voltage comparator is coupled to the output of the amplifier. A variable capacitor circuit is coupled between the input and the output of the amplifier and is coupled to the first output of the voltage comparator. A charge dump circuit has an input and an output. The input of the charge dump circuit is coupled to the second output of the voltage comparator. The output of the charge dump circuit is coupled to the input of the amplifier.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: February 13, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Sravana Kumar Goli, Nagesh Surendranath, Saugata Datta, Sandeep Oswal
  • Patent number: 11901863
    Abstract: An oscillator circuit includes a total of N (N?2) class-D oscillator circuits stacked together between a supply voltage node and a reference voltage node. The output ports of adjacent class-D oscillator circuits in the disclosed oscillator circuit are coupled together by capacitors to ensure frequency and phase synchronization for the frequency signals generated by the class-D oscillator circuits. Compared with a reference oscillator circuit formed of a single class-D oscillator circuit, the oscillation amplitude of each of the class-D oscillator circuits in the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit, and the current consumption of the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: February 13, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Simone Spataro, Salvatore Coffa, Egidio Ragonese
  • Patent number: 11903120
    Abstract: An adhesion between a sealing resin layer and a shield film is improved by a mesh sheet disposed on an opposite surface of the sealing resin layer. A radio frequency module includes a wiring board, a component mounted on an upper surface of the wiring board, a sealing resin layer that covers the component, a mesh sheet disposed on an upper surface of the sealing resin layer, and a shield film provided to cover the upper surface and side surfaces of the sealing resin layer, and the mesh sheet. The mesh sheet and the sealing resin layer, as well as the mesh sheet and the shield film are firmly in adhesion with one another. Thus, the adhesion between the sealing resin layer and the shield film can be improved.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: February 13, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Tadashi Nomura
  • Patent number: 11888484
    Abstract: A fully connected ring oscillator circuit includes a plurality of first ring oscillator loops, a plurality of second ring oscillator loops, a plurality of ring oscillators and a plurality of coupled ring oscillators. Each first ring oscillator loop extends along a first axis. Each second ring oscillator loop extends along a second axis that is transverse to the first axis and intersects each of the first ring oscillator loops. Each ring oscillator includes one of the first ring oscillator loops connected to one of the second ring oscillator loops. Each coupled ring oscillator includes two of the ring oscillators that are connected to each other through a programmable weighted coupling block.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: January 30, 2024
    Assignee: REGENTS OF THE UNIVERSITY OF MINNESOTA
    Inventors: Hyung-Il Kim, William Moy, Hao Lo
  • Patent number: 11879963
    Abstract: Disclosed herein is a tunable resonant circuit including an inductance directly electrically connected in series between first and second nodes, a variable capacitance directly electrically connected between the first and second nodes, and a set of switched capacitances coupled between the first and second nodes. The set of switched capacitances includes a plurality of capacitance units, each capacitance unit comprising a first capacitance for that capacitance unit directly electrically connected between the first node and a switch and a second capacitance for the capacitance unit directly electrically connected between the switch and the second node. Control circuitry is configured to receive an input control signal and connected to control the switches of the set of switched capacitances. A biasing circuit is directly electrically connected to the tunable resonance circuit at the first and second nodes.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: January 23, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Parisi, Andrea Cavarra, Alessandro Finocchiaro, Giuseppe Papotto, Giuseppe Palmisano
  • Patent number: 11881855
    Abstract: A superconducting integrated circuit design method based on placement and routing by different-layer JTLs comprises: cutting a bias line at a cell data interface of a cell library, and reserving a position of a via; placing and arranging cells on a logic cell layer according to a schematic circuit logic diagram; connecting clock lines of each of the cells by using a JTL and a splitter of the logic cell layer; and performing data connection on each of the cells by using JTLs of a transverse JTL routing layer and a longitudinal JTL routing layer which are not in the same layer as the logic cell layer, wherein the JTL of the transverse JTL routing layer is used as a transverse routing cell for data between the cells, the JTL of the longitudinal JTL routing layer is used as a longitudinal routing cell for data between the cells.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: January 23, 2024
    Assignee: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY CHINESE ACADEMY OF SCIENCES
    Inventors: Jie Ren, Ruo Ting Yang, Xiao Ping Gao, Zhen Wang
  • Patent number: 11876373
    Abstract: Disclosed are a power-aware method, a power-aware system and a converter. The power-aware method includes: receiving an input signal, wherein the input signal is a capacitive type, a resistive type, a voltage type or a current type, coarsely quantizing the input signal and outputting a numerical control code, the numerical control code indicating size information of the input signals, and turning on a corresponding number of power-consuming modules based on the numerical control code. By the power-aware method, the power-aware technical effect of a circuit may be provided and turned-on power-consuming modules always have the most suitable number regardless of the size of the input signals, which may ensure normal operation, and will not waste power consumption due to too many power-consuming modules and energy efficiency is improved as a whole.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: January 16, 2024
    Inventors: Le Ye, Heyi Li, Ru Huang, Yuanxin Bao, Hao Zhang
  • Patent number: 11876487
    Abstract: An oscillator includes a crystal oscillation circuit configured to generate an oscillation signal having a natural frequency, an injection circuit configured to inject a first injection signal and a second injection signal into the crystal oscillation circuit, a dithering circuit configured to transmit a first control signal for generating the first injection signal to the injection circuit, and a phased-lock loop (PLL) circuit configured to lock a phase of the first injection signal to the natural frequency, to transmit a second control signal for generating the second injection signal to the injection circuit.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehong Jung, Seungjin Kim, Seunghyun Oh
  • Patent number: 11875272
    Abstract: Compute engine circuitry configured to represent a spin network mapping of a graph representing a combinatorial optimization problem includes a plurality of ring oscillator cells, each of which includes a ring oscillator having an oscillator output, at least one coupling block, and a read block. Each coupling block connects the ring oscillator of the cell to the ring oscillator of one of a plurality of neighboring cells to form a coupled ring oscillator. The read block generates a state output for each coupled ring oscillator that indicates whether the coupled ring oscillator is in one of a same-phase state, in which the connected ring oscillators oscillate in phase with each other, and an opposite-phase state, in which the connected ring oscillators oscillate in an opposite phase from each other. A controller is configured to output a total energy of the mapping based on the state outputs.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 16, 2024
    Assignee: REGENTS OF THE UNIVERSITY OF MINNESOTA
    Inventors: Hyung-il Kim, Ibrahim Ahmed, Po-wei Chiu
  • Patent number: 11868150
    Abstract: The present invention discloses a power supply stabilizing circuit having noise suppressing mechanism configured to drive a voltage-control oscillating circuit that includes a current-adjusting N-type transistor including a drain, a source and a gate and an adjusting voltage generation circuit. The drain receives a first operation voltage. The source generates a power signal to the voltage control oscillator circuit. The gate receives an adjusting voltage. The adjusting voltage generation circuit operates according to a second operation voltage higher than the first operation voltage and receives a reference voltage that is a division of the first operation voltage to generate the adjusting voltage. The adjusting voltage is a sum of the reference voltage and a threshold voltage of the current-adjusting N-type transistor such that the current-adjusting N-type transistor operates in a saturation region to keep a current variation amount of the power signal smaller than a predetermined value.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: January 9, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Hsi-En Liu
  • Patent number: 11863301
    Abstract: The purpose of the present invention is to improve signal modulation resolution. A coarse phase modulation element 62A modulates a signal into any of M1 (M1 is an arbitrary integer) patterns in a first range. Fine phase modulation elements 62B-1 through 62B-(k?1) respectively modulate the signal into any of M2 through Mk (M2 through Mk are arbitrary integers that are independent of each other and M1) patterns in a second range through k-th range (k is an integer of 2 or greater). A coarse DAC 61A and DACs 61B-1 through 61B-(k?1) perform control such that the second range through k-th range become narrower than the first range.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 2, 2024
    Assignee: Tamagawa Academy & University
    Inventors: Ken Tanizawa, Fumio Futami
  • Patent number: 11863192
    Abstract: An apparatus includes a digitally controlled oscillator (DCO), which includes an inductor coupled in series with a first capacitor. The DCO further includes a second capacitor coupled in parallel with the series-coupled inductor and first capacitor, a first inverter coupled in parallel with the second capacitor, and a second inverter coupled back-to-back to the first inverter. The DCO further includes a digital-to-analog-converter (DAC) to vary a capacitance of the first capacitor.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: January 2, 2024
    Assignee: Silicon Laboratories Inc.
    Inventor: John M. Khoury
  • Patent number: 11863125
    Abstract: An object of the present invention is to provide a terahertz oscillator that does not have an MIM capacitor structure of which producing is intricacy, and oscillates due to resonance of an RTD and stabilizing resistors. The present invention is a terahertz oscillator, wherein a slot antenna having a slot is formed between a first electrode plate and a second electrode plate which are applied a bias voltage, stabilizing resistors to respectively connect to the first electrode plate and the second electrode plate are provided in the slot, an RTD is provided on the second electrode plate through a mesa, and a conductive material member to form an air bridge between the first electrode plate and the mesa is provided, and wherein an oscillation in a terahertz frequency band is obtained due to a resonance of the RTD and the stabilizing resistors.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: January 2, 2024
    Assignee: TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Safumi Suzuki, Van Ta Mai, Yusei Suzuki, Masahiro Asada
  • Patent number: 11855637
    Abstract: A ring oscillator includes an oscillation module, a first delay module, and a second delay module. The oscillation module is disposed in a first delay loop and a second delay loop and includes a first number of latches connected in series. The oscillation module has two input ends and two output ends, and the two input ends are respectively connected to a first node and a second node. The first delay module is disposed in the first delay loop and has an input end connected to a first output end of the oscillation module and an output end connected to the first node. The second delay module is disposed in the second delay loop and has an input end connected to a second output end of the oscillation module and an output end connected to the second node.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: December 26, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Chan Chen, Anping Qiu
  • Patent number: 11855636
    Abstract: Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: December 26, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yuxia Wang, Kai Tian
  • Patent number: 11855420
    Abstract: Methods and apparatus can be used to turn an existing 240 VAC or 480 VAC/600 VAC outlet into two or more time-sharing, i.e., one operating at a time, outlets. An AC switch box with two time-sharing outlets can be made with either a mechanical switch for switching which load receives power, or automatically, by a microcomputer system, for example. In the automatic AC switch box, the non-favored outlet may be typically powered on unless a load is detected at the favored/default outlet, when power to the non-favored outlet is automatically disconnected until the load is reduced or eliminated.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: December 26, 2023
    Inventors: Vincent Hung Nguyen, Trang Lan Do
  • Patent number: 11848644
    Abstract: A resistor-capacitor oscillation circuit includes a first group of inverters, a second group of inverters, a latch, a delay circuit, and a third group of inverters. The first group of the inverters is connected to the delay circuit and is configured to generate a first signal A and a second signal B. An input end of the second group of the inverters is connected to an enable signal EN. An output end of the second group of the inverters is connected to the latch. An output end of the delay circuit is connected to the latch. The latch is connected to the third group of the inverters and includes a first output end and a second output end. After a first clock signal FB is driven by the third group of the inverters, an output signal CLK is output by an output end of the third group.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: December 19, 2023
    Assignee: LANSUS TECHNOLOGIES INC.
    Inventors: Xiaojiao Ren, Jiashuai Guo
  • Patent number: 11846590
    Abstract: Methods, apparatuses, and systems include acquiring initial environmental information corresponding to a superconducting qubit received from a superconducting circuit, the superconducting circuit being in an environment; determining first environmental information corresponding to the superconducting qubit in response to a quantum energy level of the superconducting qubit being a first preset energy level; determining second environmental information corresponding to the superconducting qubit in response to the quantum energy level of the superconducting qubit being a second preset energy level; determining effective environmental information based on the first environmental information and the second environmental information; and determining arbitrary-order correlation information for identifying an environmental noise based on the effective environmental information and the initial environmental information.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: December 19, 2023
    Assignee: Alibaba Group Holding Limited
    Inventors: Tenghui Wang, Hsiang-Sheng Ku, Jingwei Zhou, Chunqing Deng
  • Patent number: 11843381
    Abstract: According to an aspect of the disclosure a ring-oscillator control circuit includes a voltage reference, a ring oscillator, a power supply and a supply controller. The supply controller may be configured to select the power supply among an energy storage and an energy source such as to supply the ring oscillator in function of the voltage reference.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: December 12, 2023
    Assignee: EM Microelectronic-Marin SA
    Inventors: Athos Canclini, Mario Dellea, Can Baltaci, Clement Cheung