Patents Examined by Asok Sarkar
-
Patent number: 8288805Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.Type: GrantFiled: September 9, 2011Date of Patent: October 16, 2012Assignee: Texas Instruments IncorporatedInventors: Antonio Luis Pacheco Rotondaro, Tracy Q. Hurd, Elizabeth Marley Koontz
-
Patent number: 8288798Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a buffer layer over a substrate, the buffer layer containing a first compound semiconductor that includes elements from one of: III-V families of a periodic table; and II-VI families of the periodic table. The method includes forming a channel layer over the buffer layer. The channel layer contains a second compound semiconductor that includes elements from the III-V families of the periodic table. The method includes forming a gate over the channel layer. The method includes depositing impurities on regions of the channel layer on either side of the gate. The method includes performing an annealing process to activate the impurities in the channel layer.Type: GrantFiled: January 19, 2011Date of Patent: October 16, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Matthias Passlack
-
Patent number: 8288297Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.Type: GrantFiled: September 1, 2011Date of Patent: October 16, 2012Assignee: Intermolecular, Inc.Inventors: Yun Wang, Vidyut Gopal, Imran Hashim, Dipankar Pramanik, Tony Chiag
-
Patent number: 8283254Abstract: There are provided an etching method and an etching apparatus suitable for etching an antireflection coating layer by using a resist film as a mask. The etching method includes forming the antireflection coating layer (Si-ARC layer) on an etching target layer; forming a patterned resist film (ArF resist film) on the antireflection coating layer; and forming a desired pattern on the antireflection coating layer by introducing an etching gas including a CF4 gas, a COS gas and an O2 gas into a processing chamber and etching the antireflection coating layer by the etching gas while using the resist film as a mask.Type: GrantFiled: December 23, 2010Date of Patent: October 9, 2012Assignee: Tokyo Electron LimitedInventor: Takahito Mukawa
-
Patent number: 8278204Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method different from a conventional method. One feature of the invention is that a plasma treatment is performed before forming a wiring or the like by a dropping method typified by an ink-jetting method. As the result of the plasma treatment, a surface for forming a conductive film is modified to be liquid-repellent. Consequently, a wiring or the like formed by a dropping method can be miniaturized.Type: GrantFiled: January 24, 2011Date of Patent: October 2, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinji Maekawa, Koji Muranaka
-
Patent number: 8278721Abstract: The invention provides a method for forming a contact plug, comprising: forming a gate, a sidewall spacer, a sacrificial sidewall spacer, a source region and a drain region on a substrate, wherein the sidewall spacer is formed around the gate, the sacrificial sidewall spacer is formed over the sidewall spacer, and the source region and the drain region are formed within the substrate and on respective sides of the gate; forming an interlayer dielectric layer, with the gate, the sidewall spacer and the sacrificial sidewall spacer being exposed; removing the sacrificial sidewall spacer to form a contact space, the sacrificial sidewall spacer material being different from that of the gate, the sidewall spacer and the interlayer dielectric layer; forming a conducting layer to fill the contact space; and cutting off the conducting layer, to form at least two conductors connected to the source region and the drain region respectively.Type: GrantFiled: February 24, 2011Date of Patent: October 2, 2012Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huicai Zhong, Qingqing Liang
-
Patent number: 8274011Abstract: A soldering device includes a tip member and a temperature sensor embedded within the tip member by a buckled copper pipe that is thermally conductive. A soldering device includes a tip member and a temperature sensor embedded within the tip portion by application of a crimping force that deforms the tip portion onto the temperature sensor. A soldering device includes a tip member, a heater member, and a thermally conductive wedge that is pushed into a gap between the tip member and the heater member. A soldering device includes a tip cartridge carried by a handle assembly that includes an o-ring and an o-ring cover that keeps the o-ring from falling off of the handle assembly. The o-ring cover includes a hook portion that engages a catch feature of the handle housing.Type: GrantFiled: December 4, 2009Date of Patent: September 25, 2012Assignee: Hakko CorporationInventor: Hiroyuki Masaki
-
Patent number: 8273590Abstract: Disclosed is a patterned photoresist layer on a passivation layer, formed by a lithography process with a multi-tone photomask, having a non-photoresist region, a thin photoresist pattern, and a thick photoresist pattern. The passivation layer corresponding to the non-photoresist region is removed, thereby forming vias to expose a part of a drain electrode in a TFT and a part of a top electrode in a storage capacitor, respectively. The thin photoresist pattern is then ashed to expose the passivation layer in a pixel region. Thereafter, a conductive layer is selectively deposited on the exposed passivation layer and on the sidewalls/bottoms of the vias. Subsequently, the remaining thick photoresist pattern is ashed.Type: GrantFiled: March 17, 2011Date of Patent: September 25, 2012Assignee: Chimei Innolux CorporationInventor: Cheng-Hsu Chou
-
Patent number: 8273598Abstract: A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.Type: GrantFiled: February 3, 2011Date of Patent: September 25, 2012Assignees: International Business Machines Corporation, Macronix International Co., Ltd.Inventors: Matthew J. Breitwisch, Chieh-Fang Chen, Shih-Hung Chen, Eric A. Joseph, Chung Hon Lam, Michael F. Lofaro, Hsiang-Lan Lung, Alejandro G. Schrott, Min Yang
-
Patent number: 8268659Abstract: A method for manufacturing an edge emitting semiconductor laser chip, which has a carrier substrate, an interlayer arranged between the carrier substrate and a component structure of the edge emitting semiconductor laser chip. The interlayer is adapted to provide adhesion between the carrier substrate and the component structure. The component structure has an active zone provided for generating radiation.Type: GrantFiled: January 21, 2011Date of Patent: September 18, 2012Assignee: Osram Opto Semiconductors GmbHInventors: Christoph Eichler, Volker Härle, Christian Rumbolz, Uwe Strauss
-
Patent number: 8263433Abstract: Methods of fabricating active device array and organic light emitting diode array are provided. A first pattern metal layer is formed over a substrate. An oxide semiconductor layer is formed entirely over the substrate. A first insulation layer covering the first patterned metal layer and the oxide semiconductor layer is formed entirely on the substrate. A second patterned metal layer is formed on the first insulation layer. The oxide semiconductor layer and the first insulation layer is patterned by using the second patterned metal layer as a mask to form a first patterned oxide semiconductor layer and a first patterned insulation layer. A second insulation layer is entirely formed on the substrate. A second patterned oxide semiconductor layer is formed over the second insulation layer. A third patterned metal layer is formed over the second insulation layer.Type: GrantFiled: March 18, 2011Date of Patent: September 11, 2012Assignee: Industrial Technology Research InstituteInventors: Yung-Hui Yeh, Chih-Ming Lai, Chun-Cheng Cheng
-
Patent number: 8263449Abstract: A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate.Type: GrantFiled: January 31, 2011Date of Patent: September 11, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-ha Hong, U-In Chung, Jai-kwang Shin, Jae-joon Oh, Jong-seob Kim, Hyuk-soon Choi, In-jun Hwang
-
Patent number: 8257992Abstract: A method of fabricating a pixel array is provided. A first metal layer is formed over a substrate. The metal layer is patterned to form a plurality of data lines and a plurality of drain patterns adjacent to each data line. The data lines and the drain patterns are separated from each other. An oxide semiconductor layer and a first insulation layer covering the oxide semiconductor layer are formed over the substrate. A second metal layer is formed on the first insulation layer and patterned to form a plurality of scan lines intersected with the data lines and the drain patterns. By using the scan lines as a mask, the oxide semiconductor layer and the first insulation layer are patterned to form a plurality of oxide semiconductor channels located under each scan line. Each oxide semiconductor channel is located between one data line and one drain pattern.Type: GrantFiled: March 18, 2011Date of Patent: September 4, 2012Assignee: Industrial Technology Research InstituteInventors: Yung-Hui Yeh, Chih-Ming Lai, Chun-Cheng Cheng
-
Patent number: 8252668Abstract: Provided is a photoelectric conversion device fabrication method that realizes both high productivity and high conversion efficiency by rapidly forming an n-layer having good coverage. The fabrication method for a photoelectric conversion device includes a step of forming a silicon photoelectric conversion layer on a substrate by a plasma CVD method. In the fabrication method for the photoelectric conversion device, the step of forming the photoelectric conversion layer includes a step of forming an i-layer formed of crystalline silicon and a step of forming, on the i-layer, an n-layer under a condition with a hydrogen dilution ratio of 0 to 10, inclusive.Type: GrantFiled: August 18, 2009Date of Patent: August 28, 2012Assignee: Mitsubishi Heavy Industries, Ltd.Inventors: Kengo Yamaguchi, Satoshi Sakai, Yoshiaki Takeuchi
-
Patent number: 8252662Abstract: A method for manufacturing a plurality light emitting diodes includes providing a gallium nitride containing bulk crystalline substrate material configured in a non-polar or semi-polar crystallographic orientation, forming an etch stop layer, forming an n-type layer overlying the etch stop layer, forming an active region, a p-type layer, and forming a metallization. The method includes removing a thickness of material from the backside of the bulk gallium nitride containing substrate material. A plurality of individual LED devices are formed from at least a sandwich structure comprising portions of the metallization layer, the p-type layer, active layer, and the n-type layer. The LED devices are joined to a carrier structure.Type: GrantFiled: March 29, 2010Date of Patent: August 28, 2012Assignee: Soraa, Inc.Inventors: Christiane Poblenz, Mathew C. Schmidt, Daniel F. Feezell, James W. Raring, Rajat Sharma
-
Patent number: 8241932Abstract: An LED array comprises a growth substrate and at least two separated LED dies grown over the growth substrate. Each of LED dies sequentially comprise a first conductive type doped layer, a multiple quantum well layer and a second conductive type doped layer. The LED array is bonded to a carrier substrate. Each of separated LED dies on the LED array is simultaneously bonded to the carrier substrate. The second conductive type doped layer of each of separated LED dies is proximate to the carrier substrate. The first conductive type doped layer of each of LED dies is exposed. A patterned isolation layer is formed over each of LED dies and the carrier substrate. Conductive interconnects are formed over the patterned isolation layer to electrically connect the at least separated LED dies and each of LED dies to the carrier substrate.Type: GrantFiled: March 17, 2011Date of Patent: August 14, 2012Assignee: TSMC Solid State Lighting Ltd.Inventors: Chih-Kuang Yu, Chyi Shyuan Chern, Hsing-Kuo Hsia, Hung-Yi Kuo
-
Patent number: 8242540Abstract: A device includes a silicon substrate, and a III-V compound semiconductor region over and contacting the silicon substrate. The III-V compound semiconductor region has a U shaped interface with the silicon substrate, with radii of the U shaped interface being smaller than about 1,000 nm.Type: GrantFiled: June 11, 2010Date of Patent: August 14, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu
-
Patent number: 8236694Abstract: The present invention relates to a method for manufacturing an acceleration sensor. In the method, thin SOI-wafer structures are used, in which grooves are etched, the walls of which are oxidized. A thick layer of electrode material, covering all other material, is grown on top of the structures, after which the surface is ground and polished chemo-mechanically, thin release holes are etched in the structure, structural patterns are formed, and finally etching using a hydrofluoric acid solution is performed to release the structures intended to move and to open a capacitive gap.Type: GrantFiled: September 17, 2010Date of Patent: August 7, 2012Assignee: Valtion Teknillinen TutkimuskeskusInventors: Jyrki Kiihamäki, Hannu Kattelus
-
Patent number: 8232200Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.Type: GrantFiled: March 18, 2011Date of Patent: July 31, 2012Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd., Advanced Micro Devices, Inc., Infineon Technologies AGInventors: Hyeok-Sang Oh, Woo-Jin Jang, Bum-Ki Moon, Ji-Hong Choi, Minseok Oh, Tien-Jen Cheng
-
Patent number: 8231348Abstract: A platform cooling structure for a gas turbine moving blade is provided which is capable of improving cooling performance of a platform and of improving reliability of a moving blade in such a manner that a portion in the vicinity of a side edge of the platform which is away from moving blade cooling passageways and is easily influenced by thermal stress caused by high-temperature combustion gas, that is, an upper surface of the side edge is effectively cooled by guiding high-pressure cooling air, flowing to the moving blade cooling passageways, to a discharge opening formed in a surface of the platform in the vicinity of the side edge of the platform without particularly attaching an additional member such as a cover plate to the platform. A moving blade cooling passageway 17c is formed in the inside of the gas turbine moving blade.Type: GrantFiled: November 27, 2007Date of Patent: July 31, 2012Assignee: Mitsubishi Heavy Industries, Ltd.Inventors: Shunsuke Torii, Masamitsu Kuwabara, Eisaku Ito