Patents Examined by Aurangzeb Hassan
  • Patent number: 10571880
    Abstract: An industrial controller that controls operation of an industrial system. The industrial controller comprises a processor and a memory storing instruction, wherein the instructions cause the processor to perform certain functions. In particular, the instructions cause the processor to communicate high speed data in a first industrial protocol between the industrial controller and a high speed device during a first frame section but not during a second frame section of a controller frame of the industrial controller and communicate linking device data in a second industrial protocol between the industrial controller and a linking device during the second frame section but not during the first frame section or during the third frame section of the controller frame.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: February 25, 2020
    Assignee: General Electric Company
    Inventors: John Alexander Petzen, III, Timothy John Kolb, Dana Robert Kreft, Isaac Millen Rushing
  • Patent number: 10565133
    Abstract: Methods and apparatus for reducing accelerator-memory access costs in platforms with multiple memory channels. The apparatus includes a computing platform having multiple accelerators and multiple memory devices accessed via a plurality of memory channels. Jobs are submitted via software running on the computing platform to access a function to be offloaded to an accelerator. Under the offloaded function, the accelerator accesses one or more buffers that collectively requiring access via multiple memory channels among the plurality of memory channels. Accelerators having an available instance of the function are identified, and an aggregate cost for accessing the one or more buffers via the multiple memory channels are calculated for each of the accelerators. The accelerator with the least aggregate cost is then selected to offload the function to. New Instruction Set Architecture (ISA) instructions are also disclosed to identify memory pages and memory channels used for buffers.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventor: Vinodh Gopal
  • Patent number: 10558602
    Abstract: A transmitter comprising an input data buffer to store a plurality of bytes received on a first interconnect; multiplexer circuitry coupled to the input data buffer; and an output buffer coupled to the multiplexer circuitry, a second interconnect, and a third interconnect. The multiplexer circuitry is to: receive byte enable information in the input data buffer; determine that one or more of the plurality of bytes stored in the input data buffer are invalid; store an indicator in the output buffer; store valid bytes of the plurality of bytes in the output buffer to transmit on the third interconnect; and store the byte enable information in the output buffer to transmit on the third interconnect.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventor: Israel Diamand
  • Patent number: 10540309
    Abstract: An apparatus for combining trace data from a plurality of trace sources has an input interface to receive the trace data, and an output interface to output a trace stream. A network of interconnected funnel elements combines the trace data to produce the trace stream. Each funnel element has an output port and a plurality of input ports arranged to receive trace data either from one of the trace sources, or from an output port of another funnel element in the network, and associated control circuitry to control connection of the input ports to the output port. The control circuitry determines control data indicative of a number of trace sources whose trace data is to be routed through each of the input ports of said funnel element, and controls the timing allocation of the associated funnel element's output port to each input port in dependence on the control data.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: January 21, 2020
    Assignee: ARM Limited
    Inventor: Michael John Gibbs
  • Patent number: 10521379
    Abstract: Systems and methods described herein reduce contention on shared buses through which multiple sensors send sensor readings to a computing destination by allowing different query rates for each sensor and dynamically adjusting the query rate for each sensor based on the readings that sensor reports. A first query is sent to a sensor via a bus to request a current sensor reading from the sensor. In response to the first query, the sensor sends the current sensor reading via a bus. A function of the current sensor reading, a predefined time range, and a predefined reading-value range is evaluated to determine a time interval between the first query and a second query to be sent to the sensor. When the amount of time elapsed since the first query was sent matches the time interval, the second query is sent to the sensor via the bus to request an updated sensor reading.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: December 31, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Rachel Callison, Robert R Brodeur, Robert Tappan
  • Patent number: 10521368
    Abstract: Arbitration circuitry is provided for arbitrating between requests awaiting servicing. The requests require variable numbers of resources and the arbitration circuitry permits the request to be serviced in a different order to the order in which they were received. Checking circuitry prevents a given request other than a oldest request from being serviced when a number of available resources is less than a threshold number of resources. The threshold number is varied based on the number of resources required for at least one other request awaiting servicing.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: December 31, 2019
    Assignee: ARM Limited
    Inventors: Max John Batley, Ian Michael Caulfield, Chris Abernathy
  • Patent number: 10522200
    Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 31, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10515033
    Abstract: Provided is technology simplifying managing locally connected devices. A device management system configured to connect through a network a device manager and a relay manager that connects to multiple devices through a local communication path. The device manager sends to the relay manager through the network a first process request, the first process request conforming to SNMP, and containing device identification information identifying a device that connects to the relay manager. The relay manager acquires from the first process request target identification information identifying management information to process in the management information of a device, generate a second process request containing the target identification information, and send the second process request through the local communication path indicated by the device identification information contained in the first process request.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: December 24, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Ryosuke Kakio, Masato Iguchi, Toshie Imai
  • Patent number: 10503520
    Abstract: Embodiments are generally directed to automatic waking of power domains for graphics configuration requests. An embodiment of an apparatus an interface to receive a graphics configuration request, wherein the graphics configuration request is directed to a target graphics register in a graphics domain; registers for storage of data, the registers including one or more configuration registers that are accessible for storage of the graphics configuration request; automatic power domain determination logic to determine a power domain for the target graphics register based on shared information accessed by the automatic power domain determination logic; and wake indication logic to determine whether the power domain for the target graphics register is in a reduced power state and, upon making a reduced power state determination, to generate a wake indication for the power domain.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 10, 2019
    Assignee: INTEL CORPORATION
    Inventors: William S. Dubel, Josh B. Mastronarde, Melaku Teshome
  • Patent number: 10506139
    Abstract: A reconfigurable pin-to-pin interface includes lane circuits and a reconfiguration circuit. A first lane circuit of the lane circuits obtains a first received signal by receiving a first input signal transmitted via a first lane. A second lane circuit of the lane circuits obtains a second received signal by receiving a second input signal transmitted via a second lane. When the second lane is used as one data lane and the first lane is used as one clock lane, the reconfiguration circuit redirects the first received signal to the second lane circuit for acting as an clock input of the second lane circuit. When the first lane is used as one data lane, the reconfiguration circuit blocks the first received signal from being redirected to the second lane circuit for acting as the clock input of the second lane circuit.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: December 10, 2019
    Assignee: MEDIATEK INC.
    Inventors: Li-Hung Chiueh, Man-Ju Lee, Chen-Yu Hsiao, Ching-Hsiang Chang
  • Patent number: 10503594
    Abstract: A method includes sending, by a computing device of a dispersed storage network (DSN), a set of write request messages to a set of storage units of the DSN regarding a plurality of sets of encoded data slices. The method continues by receiving, from a first storage unit, a first write response message including a group of status messages, which indicate whether a corresponding revision level of each of the first encoded data slices is a next revision level in accordance with a current revision level. The method continues by interpreting the group of status messages to determine whether an encoded data slice of first encoded data slices has a revision level error. When the error, the method continues by flagging the encoded data slices for a rollback message and when no error, the method continues by flagging each encoded data slice for a write commit message.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 10, 2019
    Assignee: PURE STORAGE, INC.
    Inventors: Andrew Baptist, Wesley Leggette, Jason K. Resch
  • Patent number: 10503681
    Abstract: An Internet Protocol (IP)-enabled smart transducer includes a sensor for generating field data regarding a physical quantity associated with processing equipment or a device in an industrial processing facility, and a signal conditioning circuit for at least one of amplifying and filtering the field data to provide conditioned field data. A communications interface is coupled to the signal conditioning circuit including a processor having an associated memory and a field data to IP data conversion algorithm for generating the IP data from the conditioned field data, and a transmitter is for transmitting the IP data across an IP bus to at least one application connected to the IP bus.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: December 10, 2019
    Assignee: Honeywell International Inc.
    Inventors: Roland Essmann, Darek Kominek
  • Patent number: 10496567
    Abstract: A wireless configurable flash memory that facilitates wireless access of data includes a storage module configured to store the data, a configurable protocol module configured to parse frames of various protocols according to a configuration parameter and a control module configured to control wireless reception and transmission of the data and parsing of wireless protocols. By means of the configurable protocol module, the value of each field defined in a protocol are reconfigurable, so that the wireless configurable flash memory can be self-adaptive to changes in the protocols, identification of protocols is converted to simple comparison on the values of respective fields of the protocols, and data of multiple protocols can be transmitted and received though a simple configurable protocol module. Thus, the wireless configurable flash memory for wireless access of the data has the characteristics of high self-adaptability, small area and low power consumption.
    Type: Grant
    Filed: October 7, 2018
    Date of Patent: December 3, 2019
    Inventor: Kefeng Zhang
  • Patent number: 10496411
    Abstract: A method is described that includes fetching an instruction. The method further includes decoding the instruction. The instruction specifies an operation, a first operand and a second operand. The method further includes fetching the first and second operands of the instruction. The first and second operands are each composed of a plurality of larger chunks having constituent elements. The method further includes performing the operation specified by the instruction including generating a resultant composed of a plurality of larger chunks having constituent elements. The generating of the resultant includes selecting for each element in the resultant a contiguous group of bits from a same positioned chunk of the first operand as the chunk of the element in the resultant, the contiguous group of bits being identified by a same positioned element of the second operand as the element in the resultant.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Tal Uliel, Robert Valentine
  • Patent number: 10474592
    Abstract: A microcontroller device comprises at least one processor (8), one or more peripheral systems (6) and a resource supply module (2). The processor (8) and peripheral system(s) (6) are each arranged to generate a signal when they require power and/or a clock signal. These signals stimulate the resource supply module (2) to supply the requested resource.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: November 12, 2019
    Assignee: NORDIC SEMICONDUCTOR ASA
    Inventors: Arne W Venas, Ragnar Haugen
  • Patent number: 10474859
    Abstract: A barcode-reading system may include a barcode reader that includes an illumination system, an image sensor, an optic system, a supercapacitor, and a first wireless point-to-point interface. The illumination system may be configured to illuminate a target area. The image sensor may be configured to capture an image of the target area. The optic system may be configured to focus reflected light from the target area onto the image sensor. The supercapacitor may be configured to provide operating power to the barcode reader. The barcode-reading system may also include a docking station configured to provide charging power to charge the supercapacitor of the barcode reader. The docking station may include a second wireless point-to-point interface. The first wireless point-to-point interface and the second wireless point-to-point interface may be configured to establish a wireless point-to-point communication link between the barcode reader and the docking station.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: November 12, 2019
    Assignee: THE CODE CORPORATION
    Inventors: Phil Utykanski, Ryan Hoobler
  • Patent number: 10474599
    Abstract: An apparatus can include a read data mover circuit adapted to fetch a portion of data for each of a plurality of read channels. The read data mover circuit is adapted to output, to an accelerator circuit, a plurality of bits of data for each of the plurality of read channels concurrently as first streamed data. The apparatus can include a controller configured to control operation of the read data mover circuit. In another aspect, the apparatus can include a write data mover circuit adapted to receive second streamed data from the accelerator circuit and output the second streamed data in a different format. The controller may be configured to control operation of the write data mover circuit.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: November 12, 2019
    Assignee: XILINX, INC.
    Inventor: Sundararajarao Mohan
  • Patent number: 10467021
    Abstract: A multi-node computer system, comprising: a plurality of nodes, a system control unit and a carrier board. Each node of the plurality of nodes comprises a processor and a memory. The system control unit is responsible for: power management, cooling, workload provisioning, native storage servicing, and I/O. The carrier board comprises a system fabric and a plurality of electrical connections. The electrical connections provide the plurality of nodes with power, management controls, system connectivity between the system control unit and the plurality of nodes, and an external network connection to a user infrastructure. The system control unit and the carrier board provide integrated, shared resources for the plurality of nodes. The multi-node computer system is provided in a single enclosure.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: November 5, 2019
    Assignee: Advanced Green Computing Machines-IP
    Inventors: Tung M. Nguyen, Syed Najaf Rizvi, David Nguyen, Adam Drobot, Eric Anderson
  • Patent number: 10459872
    Abstract: A data communication apparatus for performing communication of data with a master device via a bus includes a clock control signal generation circuit that outputs a clock control signal corresponding to a reset state and a communication state of the data communication apparatus, a communication start detection circuit that detects a start of communication on the basis of a clock signal on the bus and the data, a clock generation circuit that generates an internal clock signal on the basis of the clock signal on the bus, and a data processing control circuit that receives the internal clock signal and controls communication of the data with the master device. The clock generation circuit stops generating the internal clock signal in accordance with the clock control signal, in the reset state of the data communication apparatus and in a period from release of the reset state to the start of communication.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: October 29, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuhiro Nakamuta, Masanori Iijima
  • Patent number: 10459868
    Abstract: An expansion bridge chip for a modular chip system includes at least one upstream interface for communicating with an application processor module, a plurality of downstream interfaces for communicating with peripheral modules, and an upstream address decoder on each interface for directing data on the upstream interface to a downstream interface. In such an expansion bridge chip, each upstream interface may have a first bandwidth, each downstream interface may have a respective bandwidth, and the expansion bridge chip may be balanced, such that a sum of all respective bandwidths of the plurality of downstream interfaces is equal to the first bandwidth. Alternatively, each upstream interface may have a first bandwidth, each of the downstream interfaces may have a respective bandwidth, and the expansion bridge chip is unbalanced, such that a sum of all respective bandwidths of the plurality of downstream interfaces exceeds the first bandwidth, and interfaces contend for bandwidth.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: October 29, 2019
    Assignee: Marvell International Ltd.
    Inventor: Stephen Rowland