Abstract: A method of determining a hard disk operation status is for determining an operation status of an electronic device which comprises a SGPIO port and a hard disk. The method comprises receiving an operation status raw signal of the hard disk through the SGPIO port, determining whether receiving a previous operation status raw signal of the hard disk has been performed before an operational period before receiving the operation status raw signal, generating an operation status adjusted signal according to the operation status raw signal of the hard disk and an enabled status signal of the SGPIO port when determining that receiving the previous operation status raw signal has not been performed before an operational period before receiving the operation status raw signal, and performing a delay procedure on the operation status adjusted signal according to a preset time interval to generate and output an operation status determined signal.

Abstract: A plurality of devices communicate over a bus, the devices comprising a plurality of controller devices and a plurality of second devices. Each of the controller devices is responsible for assigning one or more of the addresses including at least the address of each of a respective one or more of the second devices. A controller device comprises address allocation logic configured to assign an address to each of that controller device's respective one or more second devices, by: searching for a currently unassigned address to assign to each of the respective one or more second devices, and if an unassigned address for one of those one or more second devices cannot be found, to issue a request to at least one other of the controller devices requesting that the other controller device changes one of the one or more addresses which that other controller device is responsible for assigning.

Abstract: A communication system, first and second device-side connectors and cable-side connectors are configured such that, when the first device-side and first cable-side connector are connected to each other, a communication line connection portion of the first device-side connector and the first cable-side connector are connected to each other, and when the second device-side and second cable-side connector are connected to each other, a communication line connection portion of the second device-side connector and second cable-side connector are connected to each other, and a valid/invalid switching circuit is configured to: in a case where the first and second cable-side connectors are connected to the first and second device-side connectors, respectively, render a connection of a termination resistor to a pair of conductors of an internal communication line invalid; and in other cases, render the connection of the termination resistor to the pair of conductors of the internal communication line valid.

Abstract: The present disclosure is directed to systems and methods sharing memory circuitry between processor memory circuitry and accelerator memory circuitry in each of a plurality of peer-to-peer connected accelerator units. Each of the accelerator units includes virtual-to-physical address translation circuitry and migration circuitry. The virtual-to-physical address translation circuitry in each accelerator unit includes pages for each of at least some of the plurality of accelerator units. The migration circuitry causes the transfer of data between the processor memory circuitry and the accelerator memory circuitry in each of the plurality of accelerator circuits. The migration circuitry migrates and evicts data to/from accelerator memory circuitry based on statistical information associated with accesses to at least one of: processor memory circuitry or accelerator memory circuitry in one or more peer accelerator circuits.

Abstract: A data recording system includes a host terminal and a data recorder. The host terminal defines a first module card to be corresponding to a first data channel and a first module card slot of the data recorder. The first module card is inserted into the first module card slot, and the data recorder stores a first type of data captured from the first data channel to the first module card. The host terminal has the data recorder stop capturing the first type of data, and defines a second module card to be corresponding to a second data channel and the first module card slot of the data recorder. The data recorder is shut down, and the first module card is dismounted from the first module card slot. The second module card is inserted into the first module card slot, and the data recorder is rebooted.

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

Abstract: A vehicle safety electronic control system (11) including master and slave microcontrollers (12, 13). The master microcontroller (12) is connected to a TDMA network bus, and the slave microcontroller (13) is connected to the master microcontroller (12) via a general purpose input/connection (14). Both microcontrollers (12, 13) are configured to operate schedule table based execution, and each has a respective synchronization counter. The master microcontroller (12) is configured to update its synchronization counter in response to a primary synchronization signal (19) from the network bus (10), and to issue a corresponding secondary synchronisation signal (20) to the slave microcontroller (13) via the general purpose input/output connection (14).

Abstract: A data storage system can employ one or more data storage modules that each have multiple constituent data storage devices. A plurality of data storage devices can be connected to a control board within a single housing with the control board having a number of SATA outputs connected to each of the plurality of data storage devices. The number of SATA outputs may be less than a total number of data storage devices in the plurality of data storage devices. Each SATA output can be connected to a separate first-tier port multiplier that has circuitry to split a single set of SATA signals into multiple duplicate sets of SATA signals.

Abstract: A subscriber station for a serial bus system is described. The subscriber station includes a communication control device for generating a message to serially transmit on the bus system, and/or for reading a message that has been serially received by the subscriber station on the bus system. The communication control device is configured to decide whether there exists, for aborting a serial transmission of the frame onto the bus line which is currently being carried out, an abortion criterion according to which a serial transmission of a higher-priority frame for a message is more important than the serial transmission of the frame onto the bus line which is currently being carried out, and to provide in the frame currently being serially transmitted, on the basis of the decision that has been made, a signalization as to whether or not the frame currently being serially transmitted is to be aborted.

Abstract: A method and input circuit unit having a first input circuit and a redundant second input circuit, wherein each input circuit includes an input for feeding a measurement current that can be obtained from a signaling device and that can be switched over and operated in such an input circuit unit, where the measurement current causes a voltage drop across a measurement resistor that can be evaluated as a measured value, where a parallel connection of the first and second input circuits causes division of the measurement current among the first and second input circuits, and where at least one input circuit include a device for compensating the decreased voltage drop across the measurement resistor resulting from the division of the measurement current.

Abstract: This disclosure describes systems, methods, and devices related to sensor data pipelining. A device may identify a first request of one or more requests received from a wireless universal serial bus (USB) host, wherein the first request is to collect data from a USB sensor. The device cause to send the first request to the USB sensor. The device identify a first response from the USB sensor, wherein the first response comprises data collected by the USB sensor based on the first request. The device determine that no additional requests are received from the wireless USB host. The device cause to send a second autonomous request to the USB sensor to collect data. The device identify a second response received from the USB sensor, wherein the second response is associated with the autonomous second request. The device cause to buffer or send the second response to the wireless USB host based on a second request being received from the wireless USB host.

Abstract: In an automation-communication network, at least one distribution node comprises input/output interfaces each connected to at least one network segment. In a first network segment a first subscriber and in a second network segment a second subscriber are arranged. Data are exchanged between the first and the second subscriber by telegrams realized as scheduled telegrams and unscheduled telegrams. The distribution node receives an unscheduled telegram on an input/output interface and sends an unscheduled telegram on a further input/output interface. The distribution node determines a transmission duration for transmission of the unscheduled telegram. The distribution node transmits the unscheduled telegram. Prior to transmission, the distribution node deposits a first telegram information in a data field. The distribution node fragments the unscheduled telegram if the telegram cannot be transmitted within a time slot.

Abstract: A method of interfacing a memory controller and a memory device in a memory system includes transmitting a control signal between the memory controller and the memory device using a time division multiplexing (TDM) communication process, and transmitting data between the memory controller and the memory device using a serializer/deserializer (SERDES) communication process. Data communication in the memory system is performed via a physical channel and a plurality of virtual channels corresponding to the physical channel.

Abstract: Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners.

Abstract: An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard. The BMC includes a serial interface. The daughterboard includes a universal asynchronous receiver/transmitter (UART) terminal, a bridging chip, and a microcontroller communicatively coupled to the BMC via the bridging chip. The BMC establishes a serial connection, through the serial interface and the UART terminal, with the microcontroller.

Abstract: Techniques for improving data transfer in a system having multiple accelerated processing devices (“APDs”) are described herein. In such a system, multiple APDs are coupled to a processor (e.g., a central processing unit (“CPU”)) via a general interconnect fabric and to each other via a high speed interconnect. The techniques herein increase the effective bandwidth for transfer of data between the CPU and the APD by transmitting data to both APDs through the portion of the interconnect fabric coupled to each respective APD. Then, one of the APDs transfers data to the other APD or to the processor via the high speed inter-APD interconnect. Although data transferred “indirectly” through the helper APD takes slightly more time to be transferred than a direct transfer, the total effective bandwidth to the target is increased due to the high-speed inter-APD interconnect.

Abstract: Methods, systems and computer program products for operating an output processor a transaction processing system are provided. Aspects include receiving a request by an output processor to deliver an output message having a plurality of message segments and obtaining a target buffer size. Aspects also include allocating an output buffer for the output message, the output buffer having the target buffer size and iteratively obtaining a message segment of the plurality of message segments and storing the message segment in the output buffer. Based on a determination that all of the plurality of message segments have been stored, aspects include delivering the output message. Based on a determination that the output buffer is full and that all of the plurality of message segments have not been stored in the output buffer, aspects further include increasing the target buffer size to a maximum buffer size.

Abstract: An access control apparatus includes a memory, and a processor coupled to the memory and configured to, in response to an access request to a storage device, output an access command through a first path to a first controller among a plurality of controllers that control the storage device, the access command being a command to access the storage device, when no response to the access command to the first controller is received before a predetermined time passes after the output of the access command, control a second controller different from the first controller among the plurality of controllers through a second path coupled to the second controller such that the second controller stops processing executed by the first controller according to the access command, and output the access command through the second path after receiving a response to the control on the second controller.

Abstract: A method and a system embodying the method for data lockdown and data overlay in a packet to be transmitted, comprising providing a first and a second masks comprising one or more position(s) and a data value at each of the one or more position(s); aligning the masks with the packet; comparing the data value at each of the one or more position(s) in the first mask with the data value at the one or more aligned position(s) in the packet; optionally replacing a data value at each of the one or more position(s) in the packet with a data value at the one or more aligned position(s) in the second mask; and providing the packet for transmission if the data value at each of the one or more position(s) in the first mask and the data value at the one or more aligned position(s) in the packet agree.

Abstract: A transmission apparatus includes a logic circuit for performing a predetermined process, and outputting a logic output signal depending on the process, an open-drain signal generation circuit, connectable at an input terminal to the logic circuit and at an output terminal to a pull-up resistor, and a transmission path failure determination circuit for determining whether there is a failure in a transmission path which transmits a signal outputted from the logic circuit via the open-drain signal generation circuit, wherein the transmission path failure determination circuit includes an edge waveform information obtaining circuit for obtaining edge waveform information indicating a waveform of at least one of a rising edge and a falling edge of an application signal, and a failure determination circuit for determining whether the edge waveform information satisfies a predetermined condition, and outputting a failure signal indicating that there is a failure in the transmission path.