Abstract: Method and computer program product for testing software subroutines in an application programming interface. In an exemplary embodiment, a C++ class hierarchy is established for creating a set of intrinsic data element objects containing values of base parameters and a set of list data element objects representing grouped data structures and the subroutines themselves by containing a root-level parameter list for the subroutine, The classes representing each type of base parameter type have associated therewith program code means for creating a user interface for editing the values of such data elements. The list class contains associated program code means for generating a dialog box to display the contents of the grouped data element and provide means to initiate editing of the individual data element values. The data element objects are created by instantiating the appropriate C++ class for a base parameter, grouped data structure, or root-level parameter list.

Abstract: There is disclosed a multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The image processor is structured with several individual processors all having communication links to several memories. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Abstract: Disclosed is a circuit for assisting programmers in developing programs to be loaded into read-only memories within microprocessor-based systems. The circuit acts as a ROM emulator and is powered by the target computer system, thus removing the need for an external power supply. The circuit may be reprogrammed by the target computer system even if the target computer system is not designed to allow write cycles to read-only memory. The software to be developed is stored in an electrically erasable programmable read-only memory, and may be reprogrammed either from the target computer system or through the parallel interface of a host computer system.

Abstract: A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit.

Abstract: In a microcomputer, a high-order address bus of a control processing unit (CPU) is coupled to a first input of an address selector and an address latch having an output coupled to a second input of the address selector. An output of the address selector is connected to one input of a multiplexer having the other input connected to a high-order data bus of the CPU and an output connected to high-order address/data bus terminals. In the case that the microcomputer is coupled to only 8-bit external memories, the high-order address is outputted through the high-order address/data bus terminals during a period of accessing the external memory, and the address latch and the address selector are controlled to output the high-order address latched in the address latch through the high-order address/data bus terminals during a period of executing no access to the external memory.

Abstract: A jacketing system automatically interfaces dissimilar program units during program execution on a computer system. Means are provided for detecting a call for execution of a second program unit having a second call standard form a first program unit having a first call standard during execution of the first program unit on the computer system. A procedure descriptor is used in the code for the first program unit and it includes a signature that defines the call standard for each incoming call to the first program unit. A bound procedure descriptor is also used in the code for each outgoing call from the first program unit and it includes a signature that defines the call standard for the target program unit. Jacketing routines are driven by the descriptors in jacketing calls between the two program units.

Abstract: A simulator tool for efficiently modeling a semiconductor transistor structure of varying channel lengths. Process simulation of a transistor structure is performed for a half NMOS transistor structure only, followed by separate computations to expand the half-structure to a full structure of varying channel lengths. Standard device simulations are then performed on the full structures to simulate electrical properties of interest, such as threshold voltage (V.sub.T) and saturation drive current (I.sub.DSAT) The tool thereby constructs a virtual model of transistor structure fabrications that can be graphically displayed to correlate process parameters with the electrical properties for use in predicting results in actual manufacturing.

Abstract: A computer-assisted method for routing breakouts includes finding a matching for a group of pins and vias, and then routing paths between matching pin-via pairs. The matching is computed efficiently and quickly by creating convex hull data structures to represent the pins and vias, and then computing a common tangent from these convex hull structures. The endpoints of the common tangent comprise matching pin-via pairs. A matching pair is routed to find a path between a pin and via pair that achieves predefined design constraints. The method can be extended to routing wire bond connections as well.

Abstract: A system for managing power consumption in a personal computer, specifically the CPU and on-board system devices. The present invention manages the power consumption of the CPU and on-board system devices (i.e., core logic) using a global event messaging scheme and an OS-Idle power event and interrupts to provide CPU power management. The CPU's low-power state is implemented such that any or a set of predetermined device interrupts will transition the CPU from low-power state to normal operation which commences at the first instruction of the interrupt handler invoked by the device interrupt. The power consumed by the platform/chipset and controller logic devices, i.e., core logic, influenced by system clocks can be managed by decreasing frequency or stopping the distributed clock(s) altogether when in low-power state.

Abstract: A technique for emulating a computer game port uses a memory manager software program to detect output instructions from a computer software program to the game port. In response to the detected output instruction, the memory manager diverts program operation to an interrupt routine wherein position data is read from a data frame and one or more game port delay times are calculated to correspond with the position of the selected positional control device. The delay times correspond with the delay times of a conventional analog joystick coupled to a conventional game port. The memory manager also detects input instructions from computer software program to the game port and diverts the computer software program to an interrupt servicing routine in which the emulated delay times are used to load a data register that is read by the computer software program.

Abstract: A method and apparatus are provided for optimizing performance of a computer system component design by performance analysis of a simulation of the design. The method of the present invention comprises providing the computer system component design to an analyzing apparatus and carrying out a simulation run of the design. During the simulation run, operation data is generated cycle by cycle, and the generated operation data is collected and stored in a log file. The log file is input to a parser and the operation data is sequentially parsed to produce parsed data. Statistical calculations are then performed on the parsed data, and the performance results are output to the designer in graphical form. The performance information can be used to enhance performance of the computer system component prior to its fabrication.

Abstract: An asynchronous and delay-insensitive data processor comprises a plurality of components communicating with each other and synchronizing their activities by communication actions on channels and buses. Each component consists of a control part and a data part. All control parts are implemented with a lazy-active-passive handshake protocol and a sequencing means called a left/right buffer that provides the minimal sequencing constraints on the signals involved. The data parts comprise novel asynchronous ALU, buses, and registers. The control parts and data parts are connected together in an asynchronous and delay-insensitive manner.

Abstract: A method and system for modifying an identification associated with and stored internally in a computer system. Software can distinguish one computer system from another based upon an identification which is typically associated with the Central Processing Unit (CPU) of the computer system. Problems arise, however, when the CPU or other component containing the identification fail, and are replaced with components having a new identification. These problems are alleviated via the use of modifiable memory by the replacement component for storing its associated identification, and a modifying unit which can reside in the replacement component, operating system, or take the form of an application program. The modifying unit is invoked and passed an encrypted key value comprising the failed identification and the replacement identification.

Abstract: In a bus control device for DMA processing/external master transfer which is carried out by a personal computer having a write back cache, a route having a high-speed buffer inserted between a data bus for peripherals and a host data bus is separately provided, data which are written back (copied) into a main memory through a write-back operation which is required when a cache memory is dirty-hit at a read-access time of a DMA device into a cache area of the main memory are also supplied to and stored in the high-speed buffer as well as the main memory, and the high-speed buffer is allowed to perform a data access with the DMA device or an external bus master. Therefore, the DMA device/external bus master are separated from the host data bus.

Abstract: A computer system capable of processing a software application having at least one unrecognizable instruction and an associated method for emulating opcode instruction exceptions. The computer system includes a local bus, processor and memory subsystems coupled to the local bus, a system bus coupled to the local bus, and an opcode exception emulator coupled to the system bus. As the processor subsystem only recognizes a particular set of instructions, the opcode instruction emulator detects those instructions to be placed on the local bus which are not included in the recognizable set of instructions and locates corresponding recognizable emulation codes stored in the memory system for transfer to the processor subsystem in place thereof.

Abstract: A method of generating power vectors to calculate power dissipation for a circuit is provided. The circuit includes both combinational logic and sequential logic circuits. The method includes removing all sequential logic circuits from the circuit. Boolean equations that describe the logical operation of the combinational logic of the circuit cells are generated. Power vectors are generated from the Boolean equations corresponding to internal and output transitions which dissipate power in the circuit. Redundant power vectors are then eliminated. The power vectors are then analyzed for "consistent" behavior with the sequential logic circuits. Operation of sequential logic circuits follow an ordered or defined sequence of events. Power vectors that are "inconsistent" with the operation of the sequential logic circuits are eliminated. The remaining power vectors are used to simulate the power dissipation of the circuit.

Abstract: An interactive logic simulation system includes a setting unit for setting at least one display format for logic simulation result information in the form of a window defined by an arbitrary display range by interacting with a user through a display screen; a first management table for managing the display mode of a free-format display format set by the setting unit; a second management table for managing the display mode of a stream display format as a time series display format of the logic simulation result information; a third management table for managing time series data of signal values for each signal terminal constituting the logic simulation result information; and a result display control unit for specifying the logic simulation result information by using management data from the first, second and third management tables, and for displaying the logic simulation result information so specified on the display screen.

Abstract: A logic circuit simulator includes a set of programmable logic devices (PLDs) having input/output terminals connected to a hold and switch (HAS) device via a parallel bus. Each PLD includes an addressable input register for receiving and storing input data conveyed on the parallel bus and an addressable output buffer for placing its output data on the parallel bus. On each pulse of an input design clock signal each PLD simulates a separate portion of the logic, producing each bit of its output data as a logical combination of bits of its stored input data. Between design clock pulses, the HAS device successively acquires output data produced by the PLDs, rearranges the PLD output data to produce new input data for each PLD, and then successively transmits the new PLD input data words to the appropriate PLDs for storage in their input registers. The process is repeated for each cycle of the design clock signal.

Abstract: A given interconnect of a programmable gate array includes a programmable repeater circuit that enables selective isolation and testing of a select block of configured circuitry within the programmable gate array. The programmable repeater circuit includes an input node coupled to a first portion of the given interconnect and an output node coupled to a second portion of the given interconnect. A selective buffer circuit selectively outputs a buffered output signal to the output node that is related to a logic state at the input node. A signal storage circuit is also connected to the input node for selectively storing the logic state received from the input node. In a further embodiment, the signal storage circuit comprises an LSSD register. A primary latch of the LSSD register receives data selectively either from the input node, in accordance with a first clock signal, or alternatively from a secondary serial input node, in accordance with a second clock signal.

Abstract: Simulation apparatus for displaying three-dimensional graphics including a device for emitting an aroma generating material in connection therewith and a dispensing apparatus for emitting the aroma generating material.