Abstract: A cluster file system is disclosed. A plurality of disk servers, operating as a single distributed disk server layer, are connected to the one or more physical disks. Each disk server stores metadata for each of the files. A plurality of lock servers, having one or more locks for each file and associated file system metadata operates as a single centralized distributed lock server to coordinate access to the files stored by the disk server layer. A plurality of asynchronous file servers, operating as a single distributed file server layer in response to a request for a file from a user program: (i) retrieves the requested file from the disk server layer and at least one lock, associated with the retrieved file, from the lock server, and (ii) retrieves metadata for at least one file that is related to the requested files, and at least one lock, for each file that has had its metadata retrieved.

Abstract: An optical disc drive includes a firmware memory, a buffer memory, and a system control chip. The system control chip includes a processor and a memory update controller. When the optical disc drive is under a normal mode, the memory update controller is in an idle state. The processor controls the optical disc drive to fetch an update firmware from an optical disc and store the update firmware into the buffer memory. When the optical disc drive is under a firmware update mode, the processor is in an idle state. The memory update controller fetches the update firmware from the buffer memory and stores the update firmware into the firmware memory without the processor executing an update routine code.

Abstract: The queue execution mode is selected based on the unique tag that is assigned to the command. In one method embodiment a tag is assigned for each of several disc access commands sent by the host. Two or more queues are created, each having a queue execution mode. Which of the queues is assigned to the command depends on the command's tag. One device embodiment comprises a data storage disc, a memory, and a controller. The memory is configured to hold several pending commands for accessing the disc(s),each of the commands having a unique tag. The controller is configured to execute each queued command according to a mode that is determined base on the command's tag.

Abstract: We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory interface to manipulate data from at least two memory channels, each memory channel corresponding to a portion of a distributed memory, responsive to the predetermined memory access command. The memory interface includes a plurality of memory controllers coupled to the command bus, each memory controller being operable to control a corresponding memory channel responsive to the predetermined memory access command, and a push arbiter coupled to each memory controller. The push arbiter being is operable to merge and align data retrieved responsive to each split read align command.

Abstract: An information processing device and information processing method including a management table that includes three pages. A pair of first and second pages is alternately used as a valid page and an invalid page to secure the data. The valid page is copied to a third page. Even when the power is shut off in the process of updating the page, at the next start time, the status of the data writing operation when the power is shut off is determined based on the validity and stability of the pages. Therefore, the data is restored without any corruption of valid page by using a proper restoring method.

Abstract: A method of selecting logical volumes that are the targets for data migration to equilibrate the load on a system, based on the accessing data of the physical drives and logical drives under the disk array controllers, without increasing the load of the disk array controller. An external manager communicates with two or more disk array controllers, gathers and manages the access data and the configuration data relating to the physical drives and logical volumes of each disk array controller, and prepares an optimum data migration instruction to equilibrate the access load.

Abstract: An automated data library system employing a plurality of cartridges, one or more cartridge storage slots and an inventory controller. Each cartridge includes a cartridge memory. The cartridge storage slot(s) is(are) physically configured to store the cartridges. The inventory controller is operable to generate an inventory of the cartridges as stored within the cartridge storage slot(s). A generation by the inventory controller of the inventory of the cartridges as stored within the cartridge storage slot(s) involves the inventory controller simultaneously accessing cartridge identification information on two or more cartridge memories, and generating the inventory including two or more cartridges corresponding to the cartridge identification information.

Abstract: Methods and apparatus are disclosed to prefetch memory objects. An example method includes identifying program states associated with an executing program; associating memory profiles with respective ones of the program states; identifying at least one next probable state based on calculated entropy values; and prefetching memory objects associated with the at least one memory profile corresponding to the at least one next probable state.

Abstract: A multi-interfaced memory device includes an array of memory cells having a first interface and a second interface. The first interface and the second interface share an address bus and a data bus. One of the interfaces may be a random access memory interface and the second interface may be a paged access interface.

Abstract: A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.

Abstract: A system page is implemented to provide direct access to operating system data structures by user tasks. Frequently accessed data structures are located in the system page, and may be linked against during linking. The system page memory locations are mapped into user tasks as read-only memory locations, allowing read-only memory accesses during run-time. The system page reduces execution overhead without sacrificing system security.

Abstract: A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.

Abstract: A method and system for rapid data-fragmentation analysis of a New Technology File System (NTFS) is described. In one embodiment, the Master File Table (MFT) associated with a NTFS volume is analyzed to estimate the extent of data fragmentation on the NTFS volume, the analysis being performed substantially without using directory index information associated with the NTFS volume.

Abstract: A hierarchical memory access control distinguishes between blocks of data that are known to be sequentially accessed, and the contents of each block, which may or may not be sequentially accessed. If the contents of a block are provided in a sequential manner within the block, but the sequence does not correspond to a higher-level sequence, due to a non-zero offset in the start of the sequence within the block, the memory access control is configured to optimize the use of available memory by signaling when the within-block sequence corresponds to the higher-level sequence. While the within-block sequence differs from the higher-level sequence, access to the buffer is limited to the higher-level partitioning of the buffer. When the within-block sequence corresponds to the higher-level sequence, access to the buffer is provided at the within-block partitioning of the buffer.

Abstract: A technique enables creation and use of a writable, read-only snapshot of an active file system operating on a storage system, such as a multi-protocol storage appliance. The writable, read-only snapshot comprises a read-only “image” (file) residing in a snapshot and a writable virtual disk (vdisk) residing in the active file system. The writable vdisk is a “shadow” image of the snapshot file image and, as such, includes an attribute that specifies the snapshot file as a backing store.

Abstract: Various aspects of the low cost line buffer system allow a reduction in circuitry versus conventional approaches to line buffer design. A plurality of line buffers such that the output of one line buffer in the plurality of line buffers may be coupled to an input of a succeeding line buffer in the plurality of line buffers. A first line buffer in the plurality of line buffers may be coupled to an input write data signal, while the width of a subsequent plurality of line buffers may be less than or equal to the width of the previous line buffers in the plurality of line buffers.

Abstract: An object of the present invention is to provide a storage system which is shared by a plurality of application programs, wherein optimum performance tuning for a cache memory can be performed for each of the individual application programs. The storage system of the present invention comprises a storage device which provides a plurality of logical volumes which can be accessed from a plurality of application programs, a controller for controlling input and output of data to and from the logical volumes in response to input/output requests from the plurality of application programs, and a cache memory for temporarily storing data input to and output from the logical volume, wherein the cache memory is logically divided into a plurality of partitions which are exclusively assigned to the plurality of logical volumes respectively.

Abstract: A single lock word comprises an identifier field for storing a thread identifier associated with a first thread obtaining a lock on an object; an inflation field for storing a fat lock bit upon inflation of the lock on the object; and a contention field for storing a contention bit in response to an attempt by a second thread to obtain a lock on the object. The values of the single lock word are verified with a single memory fetch instruction. When unlocking an object, a single memory fetch instruction can be used to read the lock word to: (1) determine whether thread T is still the current owner of the lock, and (2) determine the states of inflation and/or contention (i.e., determine whether the fat lock and/or contention bits have been set).

Abstract: A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.

Abstract: A device is disclosed for storing mapping information for mapping a logical block address identifying a block being accessed by a host to a physical block address, identifying a free area of nonvolatile memory, the block being selectively erasable and having one or more sectors that may be individually moved. The mapping information including a virtual physical block address for identifying an “original” location, within the nonvolatile memory, wherein a block is stored and a moved virtual physical block address for identifying a “moved” location, within the nonvolatile memory, wherein one or more sectors of the stored block are moved. The mapping information further including status information for use of the “original” physical block address and the “moved” physical block address and for providing information regarding “moved” sectors within the block being accessed.