Patents Examined by Bac H. Au
  • Patent number: 10896846
    Abstract: Methods for forming conductive regions of a metallization network with reduced leakage current and capacitance are described. Aspects of the invention include forming a trench in a dielectric material on the substrate, forming a first liner layer in a first portion of the trench, forming a second liner layer in a second portion of the trench, and forming a conductive material over the second liner layer in the trench.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raghuveer Patlolla, Cornelius Brown Peethala, Chih-Chao Yang
  • Patent number: 10886231
    Abstract: A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai, Chen-Hua Yu
  • Patent number: 10879395
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin structure, and a second fin structure. The method includes forming a gate structure over the first fin structure and the second fin structure. The method includes forming a first source structure and a first drain structure on the first fin structure and on two opposite sides of the gate structure. The first source structure and the first drain structure are made of an N-type conductivity material. The method includes forming a cap layer over the first source structure and the first drain structure. The cap layer is doped with a Group IIIA element, and the cap layer adjacent to a top surface of the first source structure is thicker than the cap layer adjacent to a bottom surface of the first source structure.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10872775
    Abstract: A method is for plasma etching one or more dicing lanes in a silicon substrate having a backside metal layer attached thereto. The method includes performing a main etch using a cyclical plasma etch process in which a deposition step and an etch step are alternately repeated to produce dicing lanes having scalloped sidewalls, and switching to performing a secondary etch using a cyclical plasma etch process in which a deposition step and an etch step are alternately repeated until the backside metal layer is reached. The amount of silicon removed in one etch step during the secondary etch is half or less than half of the amount of silicon removed in one etch step during the main etch.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: December 22, 2020
    Assignee: SPTS Technologies Limited
    Inventors: Oliver J Ansell, Martin Hanicinec, Janet Hopkins
  • Patent number: 10870574
    Abstract: The present disclosure involves forming a method of fabricating a Micro-Electro-Mechanical System (MEMS) device. A plurality of openings is formed in a first side of a first substrate. A dielectric layer is formed over the first side of the substrate. A plurality of segments of the dielectric layer fills the openings. The first side of the first substrate is bonded to a second substrate that contains a cavity. The bonding is performed such that the segments of the dielectric layer are disposed over the cavity. A portion of the first substrate disposed over the cavity is transformed into a plurality of movable components of a MEMS device. The movable components are in physical contact with the dielectric the layer. Thereafter, a portion of the dielectric layer is removed without using liquid chemicals.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chuan Tseng, Chang-Ming Wu, Shih-Chang Liu, Yuan-Chih Hsieh
  • Patent number: 10867845
    Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Ching-Hwanq Su, Liang-Yueh Ou Yang, Ming-Hsing Tsai, Yu-Ting Lin
  • Patent number: 10868112
    Abstract: A circuit device includes core circuitry. The circuit device further includes a guard ring surrounding the core circuitry. The guard ring includes a first plurality of fin structures arranged in a first direction parallel to a first side of the core circuitry, wherein adjacent fin structures of the first plurality of fin structures are separated by a first distance. The guard ring further includes a second plurality of fin structures arranged in a second direction parallel to a second side of the core circuitry, wherein adjacent fin structures of the second plurality of fin structures are separated by a second distance, and the second distance is smaller than the first distance.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Wun-Jie Lin, Yu-Ti Su, Bo-Ting Chen, Jen-Chou Tseng, Kuo-Ji Chen, Sun-Jay Chang, Min-Chang Liang
  • Patent number: 10867913
    Abstract: A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Hsu Wu, Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue, Tien-I Bao
  • Patent number: 10861836
    Abstract: Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jiun Yi Wu
  • Patent number: 10861833
    Abstract: A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 8, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Tonedachi
  • Patent number: 10854546
    Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: December 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kosuke Yanagidaira, Chikaaki Kodama
  • Patent number: 10854605
    Abstract: A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Li Chiang, Cheng-Yi Peng, Tsung-Yao Wen, Yee-Chia Yeo, Yen-Ming Chen
  • Patent number: 10847517
    Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including of an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: November 24, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tsuo-Wen Lu, Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan
  • Patent number: 10840331
    Abstract: A semiconductor device includes active patterns protruding from a substrate and an insulation structure surrounding lower portions of the active patterns. The insulation structure includes an insulation layer conforming to a top surface of the substrate and to sidewalls of the active patterns and a buried insulation pattern on the insulation layer.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Guyoung Cho, Dae-Young Kwak, Shinhye Kim, Koungmin Ryu, Sangjin Hyun
  • Patent number: 10840224
    Abstract: Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jiun Yi Wu
  • Patent number: 10825735
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate. The substrate includes an active region and a blank region disposed adjacent to the active region. The method also includes forming a fin material layer on the substrate. Further, the method includes forming a plurality of fins on the active region, and a plurality of dummy fins on the blank region by etching the fin material layer. A spacing between a fin and an adjacent dummy fin is greater than a spacing between adjacent fins.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: November 3, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Qing Peng Wang
  • Patent number: 10825719
    Abstract: A method for fabricating silicon-on-insulator (SOI) semiconductor devices, wherein the piezoresistive pattern is defined within a blanket doped layer after fusion bonding. This new method of fabricating SOI semiconductor devices is more suitable for simpler large scale fabrication as it provides the flexibility to select the device pattern/type at the latest stages of fabrication.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: November 3, 2020
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Alexander A. Ned, Sorin Stefanescu, Joseph R. VanDeWeert
  • Patent number: 10818597
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric structure over a substrate, and a first interconnect structure arranged within the dielectric structure. A lower interconnect structure is arranged within the dielectric structure. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials. The first interconnect structure continuously extends from directly over a topmost surface of the lower interconnect structure facing away from the substrate to along opposing outer sidewalls of the lower interconnect structure.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiang-Wei Liu, Tai-I Yang, Cheng-Chi Chuang, Tien-Lu Lin
  • Patent number: 10811497
    Abstract: A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: October 20, 2020
    Assignee: Silanna Asia Pte Ltd
    Inventors: Vadim Kushner, Nima Beikae
  • Patent number: 10811274
    Abstract: A method of etching selectively etches a first region of a substrate with respect to a second region of the substrate formed of a different material from the first region. A deposition film is formed of a chemical species included in plasma generated from a first gas. A gaseous precursor is supplied to the substrate having the deposition film formed thereon to form an adsorption film on the substrate from the precursor. Ions from plasma generated from a second gas are supplied to the substrate having the deposition film and the adsorption film formed thereon so as to cause a reaction between the material of the first region and a chemical species included in the deposition film, so that the first region is etched. The adsorption film reduces the etching rate of the second region during the etching of the first region.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 20, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Takayuki Katsunuma