Abstract: A method of removing salt from seawater to produce potable freshwater. Apparatus that may be used with the method includes a large metal cylinder, with open top and bottom ends, anchored to the sea floor offshore. Several pressure hulls may be attached to the side of the cylinder. Within each pressure hull there are several reverse osmosis devices (“RODs”), each containing a membrane that will allow water molecules, but not sodium and chlorine ions, to pass through. Due to the pressure differential, freshwater passes through the membranes by reverse osmosis, and is pumped out of the pressure hulls to a storage facility onshore. After equilibrium is reached, the pumps for the brine can be turned off, as gravity will cause brine to flow down from the pressure hulls through an opening in the bottom of the cylinder. Alternatively, a reverse osmosis system may be supported on an elevated undersea platform.

Abstract: A tetragonal prism having a rectangular cross section is attached, as a linear motor movable section, to a moving plate to which a screw is attached rotatably and also immovably in an axial direction. A magnet is attached to each surface of the movable section. A hole section is provided in an outer frame. A linear motor coil is provided on the linear motor fixed section so that it may face the magnet on the surface of the movable section. A screw shaft is rotated by a motor through a measuring shaft penetrating a center of the movable section. By driving the linear motor comprising the magnet and the coil corresponding to each other, the screw is moved and injected in an axial direction. The fixed section is detachable and a gap between the magnet and the coil can be easily adjusted.

Abstract: An injection molding system for molding a hollow plastic article employs a hollow mold core having a longitudinal axis and a core runner cavity that has a uniform cross section throughout and which extends to the open end of the mold core. The mold core includes at least one core ejection gate and at least one core inlet gate leading from the outer surface of the core wall to the core runner cavity. When molding is performed in stages, there is it least one core ejection gate for each stage of molding. The core is clamped in between separate sets of molding blocks for each stage of molding. A core end closure cap having a core extension cavity aligned with the core runner cavity is used to close the open end of the mold core. A molten plastic is injected into the outer molding blocks and is confined to travel through the core inlet gate of the core without entering the mold cavity directly so that the molten plastic is forced to pass through the core runner cavity in order to reach the core ejection gates.

Abstract: In a process using a hot phosphoric acid etchant (12) to etch silicon nitride on a semiconductor wafer (15) submerged in a tank (11) of the etchant (12), a recirculating path is established for the etchant (12). A porous filter (35) is coated with silicon nitride and installed in the recirculating path. As the etchant (12) in the recirculating path flows through the porous filter (35), the silicon nitride on the porous filter (35) dissolves into the etchant (12). In the tank (11), the silicon nitride dissolved in the etchant (12) significantly suppresses the etch of silicon dioxide on the semiconductor wafer (15), thereby enhancing the etch selectivity of the process. Monitoring and maintaining the concentration of the silicon nitride in the etchant (12) stabilizes the etch selectivity of the process.

Abstract: A method for forming a uniformly planarized structured in a semiconductor wafer forms metal structures on a substrate layer with spaces between the structures. The top surfaces of the metal structures lie within a common plane. Dielectric material is deposited on the layer, the metal structures and in the spaces. The dielectric layer is first etched so that the dielectric material in the spaces is below the common plane. Additional dielectric material is then deposited on the layer, the metal structures and in the spaces. The dielectric layer is then subjected to a second etching. Further deposition and etching steps are performed until the top of the dielectric layer and the top surfaces of the metal structures have a common, substantially uniform planarization.

Abstract: A method of forming structures in semiconductor devices through a buffer or insulator layer comprises the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by CMP.

Abstract: A method of manufacturing an electronic device, in particular but not exclusively a semiconductor device, in which method a substrate (2) is placed inside a process chamber (1) and a surface (3) of the substrate (2) is subjected to an ozone treatment comprising the steps of: providing a liquid onto the surface (3) of the substrate (2) via first supply means, introducing a solution comprising a liquid carrier solvent and ozone gas into the process chamber (1) via second supply means, without bringing about direct contact between the solution and the surface (3) of the substrate (2).

Abstract: A process for planarization of a flash memory cell is described. A first polysilicon pattern having a top is formed over a substrate. A high-density plasma (HDP) oxide layer is deposited on the first polysilicon pattern, wherein the HDP oxide layer has a protuberance over the first polysilicon pattern. The HDP oxide layer and the first polysilicon pattern are partially etched by a sputtering etch technology. In this etching step, the protuberance is removed, the first polysilicon pattern is lowered, and the top of the first polysilicon pattern is rounded. A second polysilicon pattern covering the first polysilicon pattern is formed, wherein the second polysilicon pattern is wider than the first polysilicon pattern.

Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Abstract: The invention provides a method of making UV<200 nm transmitting optical fluoride crystals for excimer laser lithography optics and a multicompartment container for growing optical fluoride crystals, comprising a number of graphite bowls that are placed on top of one another to form a stack and which have a central conical orifice in the bottom of each of them, and also comprising a seeding unit that has a central cylindrical orifice and is arranged under the lowermost bowl, characterized in the each bowl is fitted with a heat-removing device that is made in the form of a graphite cylinder with a central conical orifice, is mounted under the bottom of each bowl, and adjoins, with its other surface, the cover of the next bowl down, in which design the cover of each bowl, apart from the uppermost one, has a central conical orifice.

Abstract: The invention relates to methods and compositions for making a multi-layer article. The compositions can be used in relatively fast methods which can superconductor material intermediates that have relatively few cracks and/or blisters. The compositions can have relatively low water contents.

Abstract: A method of manufacturing a thin-film magnetic head allowing dimension control of the width of the magnetic pole and reduction of the time required for formation is provided. A layer of iron nitride formed by sputtering is selectively etched with the RIE to form a top pole tip. In this etching process with RIE, chlorine-type gas is selected as a gas seed for etching, and the process temperature is in a range of 50° C. to 300° C. Subsequently, using part of a first mask and a tip portion of the top pole tip as a mask, part of both the write gap layer and the second bottom pole are etched with the RIE similarly to the above process, to thereby form a magnetic pole. The etching conditions are optimized by performing the process with the RIE under the above conditions, so that both of the top pole tip and the magnetic pole can be formed with high precision, and that the time required for forming both of these elements can be significantly reduced.

Abstract: A method for forming HSG polysilicon with reduced dielectric bridging and increased capacitance. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a reduced temperature to cause a nucleation of the second polysilicon layer. Grains are formed on the surface of the second polysilicon layer as a result of the nucleation. Next a wet etch is performed to remove portions of the polysilicon grains and portions of the first polysilicon layer. The duration of the wet etch is controlled to retain a roughened surface area. The size of the grains decreases during the wet etch and the distance between the grains increases. A dielectric layer is deposited to overlie the rough polysilicon following the wet etch. The thickness of the dielectric layer tends to be uniform thereby reducing bridging of the dielectric between the grains of the of the polysilicon.

Abstract: An ingot is manufactured by pulling it up such that V/Ga and V/Gb become 0.23 to 0.50 mm2/minute ° C., respectively, where V (mm/minute) is a pulling-up speed, and Ga (° C./mm) is and axial temperature gradient at the center of the ingot and Gb (° C./mm) is an axial temperature gradient at the edge of the ingot at temperatures in a range of 1,300° C. to a melting pointy of silicon. A wafer obtained by slicing the ingot is heat treated in a reductive atmosphere at temperature in a renge of 1,050° C. to 1,220° C. for 30 to 150 minutes. A silicon wafer free of OSF's, free of COP's, and substantially free of contamination such as Fe and of occurence of slip, is obtained.

Abstract: The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a polysilicon layer for a dummy gate on a wafer; forming an interlayer insulating layer on the wafer; polishing the interlayer insulating layer to expose a top surface of the dummy polysilicon layer; and wet etching the exposed dummy polysilicon layer using a spin etching process.

Abstract: A method of manufacturing a microstrip termination is provided, the microstrip termination containing a transmission line, a tapered edge ground and a thin film resistor connecting a transmission line to the tapered edge ground. Circuits are manufactured by first cutting holes in a substrate forming alignment holes for dicing the substrate into separate circuits. A saw is then used to cut tapered grooves along the alignment holes for forming tapered edges. The substrate is then plated and etched to form the transmission lines, thin film resistors, and ground planes. Finally, the substrate is diced into the separate termination circuits.

Abstract: A method and apparatus for fabricating thin Group III nitride layers as well as Group III nitride layers that exhibit sharp layer-to-layer interfaces are provided. According to one aspect, an HVPE reactor includes one or more gas inlet tubes adjacent to the growth zone, thus allowing fine control of the delivery of reactive gases to the substrate surface. According to another aspect, an HVPE reactor includes both a growth zone and a growth interruption zone. According to another aspect, an HVPE reactor includes a slow growth rate gallium source, thus allowing thin layers to be grown. Using the slow growth rate gallium source in conjunction with a conventional gallium source allows a device structure to be fabricated during a single furnace run that includes both thick layers (i.e., utilizing the conventional gallium source) and thin layers (i.e., utilizing the slow growth rate gallium source).

Abstract: A coated article is prepared by furnishing an article substrate having a free sulfur content of less than about 1 part per million. The low-sulfur article may be made of a material selected to have a low sulfur content, provided with a scavenging element that reacts with free sulfur to produce a sulfur compound, or desulfurized by contact with a reducing gas such as hydrogen. A platinum-group metal layer is deposited over the article substrate, and a ceramic coating is applied over the platinum-group metal layer.

Abstract: A single mask process is described for making a trench type fast recovery process. The single mask defines slots in a photoresist for locally removing strips of nitride and oxide from atop silicon and for subsequently etching trenches in the silicon. A boron implant is carried out in the bottoms of the trenches to form local P/N junctions. The oxide beneath the nitride is then fully stripped in the active area and only partly stripped in the termination area in which the trenches are wider spaced than in the active area. Aluminum is then deposited atop the active area and in the trenches, but is blocked from contact with silicon in the active area by the remaining nitride layer.

Abstract: A crystal growth station including a cylindrical crucible having powered bottom and top resistance heaters mounted below and above the crucible, respectively. A supplemental heating unit is positioned around the bottom edge of the crucible. The supplemental heating unit may be unpowered or powered to heat it independently of the top and bottom heaters. If unpowered, then the supplemental heating unit is formed of a cylinder around the lower portion of the crucible side wall and a washer shaped disk member extending under part,of the crucible bottom wall. The supplemental heating unit is generally wedge shaped. The supplemental heating unit is heated by radiation from the bottom heater. The heat is conducted from the disk to the cylinder. A supplemental heater may be similarly used at the top edge of the crucible. If powered, the cylinder and the disk have slits therein to form current paths.