Abstract: In accordance with a first aspect, a susceptor is provided that includes (1) a supporting surface adapted to support a substrate, the supporting surface comprising a first material; and (2) a support frame encased within the first material, the support frame comprising a second material that has a lower coefficient of thermal expansion than the first material. The support frame is offset from a center of the susceptor toward the supporting surface. In accordance with a second aspect, a susceptor is provided that includes (1) a supporting surface adapted to support a substrate, the supporting surface comprising a first material; and (2) a support frame encased within the first material, the support frame comprising a second material that has a higher coefficient of thermal expansion than the first material. The support frame is offset from a center of the susceptor away from the supporting surface. Other aspects are also provided.

Abstract: There is provided a metal etching mask fabrication method. Chrome is first sputtered on a silica layer and a photoresist, which is thicker than the chrome layer, is deposited on the chrome layer. The photoresist layer is patterned, a first nickel is sputtered on the photoresist pattern layer and onto a first portion of the chrome layer exposed by the patterning. A second nickel layer is formed on the portions of the first nickel layer in contact with the first portion of the chrome layer by electroplating. The photoresist pattern has side walls having acute angles to prevent contact between the first nickel layer on the photoresist and the second nickel layer on the first portion of the chrome layer. The photoresist pattern layer and the first nickel layer formed on the photoresist pattern layer are removed using a solvent, and the chrome layer is removed by dry etching in plasma using a gas.

Abstract: A crystal growth method includes forming a mask layer capable of impeding crystal growth on a substrate in such a way a first nitride semiconductor layer has irregularities at a surface thereof exposed at a window region opened at a part of the mask layer, and growing a second nitride semiconductor layer over a region including the surface of the mask layer through crystal growth from the irregularities. Through-type dislocations can be reliably prevented from propagation due to the discontinuity of crystals at the irregularities and also to lateral crystal growth.

Abstract: A device isolation process flow for an atomic resolution storage (ARS) system inserts device isolation into a process flow of the ARS system so that diodes may be electrically insulated from one another to improve signal to noise ratio. In addition, since most harsh processing is done prior to depositing a phase change layer, which stores data bits, process damage to the phase change layer may be minimized.

Abstract: An etchant for etching at least one of a titanium material and silicon oxide includes a mixed liquid of HCl, NH4F and H2O. When the etchant has a NH4F/HCl molar ratio of less than one, only the titanium material is etched. When the etchant has a NH4F/HCl molar ratio of more than one, only silicon oxide is etched. When the etchant has a NH4F/HCl molar ratio of one, the titanium material and silicon oxide are etched at the same rate.

Abstract: A method for forming a low dielectric constant insulator in a monolithic substrate and the dielectric formed by the method. The method includes formation and patterning of a mask on a silicon substrate followed by anisotropic etching of the silicon to provide a dense array of deep holes. Isotropic etching may be used to form a cavity beneath the dense array of holes and coupling to bottoms of the holes. Sides of the holes are then thermally oxidized. A conventional dielectric is then formed, sealing tops of the holes. The conventional dielectric is optionally densified. Conventional chemical-mechanical polishing then planarizes the dielectric and further conventional processing may be carried out on the wafer to form active circuitry together with passive components such as high Q inductors.

Abstract: A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.

Abstract: Provided is a technique for fabrication of STIs in a semiconductor device using implantation of damaging high-energy ions to insulating material overburden to generally and/or selectively increase insulation overburden removal rates. This technique avoids the use of chemical mechanical planarization (CMP) with a combination of implantation and, in some instances, low cost batch etching. The electrical characteristics of devices created with the new technique match closely to those fabricated with the standard CMP-based technique.

Abstract: A method of manufacturing a semiconductor device provided with a first insulating film and a barrier film on a conductive region and an opening portion in the first insulating film and the barrier film, the method comprising the steps of: forming a first opening portion in the barrier film reaching the first insulating film; forming a second insulating film at least on the first insulating film in the first opening portion; and forming a second opening portion smaller than the first opening portion and reaching the conductive region by simultaneously boring a hole into the first insulating film and the second insulating film in the first opening portion.

Abstract: A technique and apparatus is disclosed for the optical monitoring and measurement of a thin film (or small region on a surface) undergoing thickness and other changes while it is rotating. An optical signal is routed from the monitored area through the axis of rotation and decoupled from the monitored rotating area. The signal can then be analyzed to determine an endpoint to the planarization process. The invention utilizes interferometric and spectrophotometric optical measurement techniques for the in situ, real-time endpoint control of chemical-mechanical polishing planarization in the fabrication of semiconductor or various optical devices.

Abstract: A method for fabricating a semiconductor device of the present invention comprises the steps of: a) depositing a masking film on a first compound semiconductor layer formed on a semiconductor substrate; b) patterning the masking film so that the film has an opening; c) etching away at least an uppermost part of the first semiconductor layer, which part is located inside the opening and includes a degraded layer formed in the step a) or b), using a first etchant and the masking film; and d) patterning the first semiconductor layer by etching away another part of the first layer using a second etchant and the masking film. That another part is located inside the opening and does not include the uppermost part with the degraded layer. The second etchant allows for etching the first layer at a rate lower than a rate realized by the first etchant.

Abstract: Provided is a method of etching a silicon nitride film, which comprises subjecting the silicon nitride film located on copper to dry etching using a mixture of fluorocarbon gas and an inert gas as the reaction gas, the fluorocarbon gas containing CF4 and CHF3 supplied at flow rates in a ratio of 3:7 to 0:1 or contains CF4 and CH2F2 supplied at flow rates in a ratio of 2.5:1 to 0:1, thereby suppressing the formation of copper fluoride.

Abstract: The present invention provides a method for the simultaneous removal of an oxygen and/or nitrogen-containing dielectric antireflective coating (“DARC”) during plasma etching of an underlying layer in a film stack. According to the method of the invention, the film stack is etched using a plasma containing reactive fluorine species. The concentration of reactive fluorine species within the plasma is controlled based on one or more of the following factors: the oxygen content of the antireflective coating, the nitrogen content of the antireflective coating, the thickness of the antireflection coating layer, and the thickness of the underlying film stack layer. The disclosure of the invention provides preferred combinations of plasma source gases which provide for the simultaneous removal of an oxygen and/or nitrogen-containing DARC layer during etching of an underlying etch stack layer, where the underlying stack layer comprises a metal silicide, polysilicon, or a metal.

Abstract: A semiconductor wafer is processed while being supported without mechanical contact. Instead, the wafer is supported by gas streams emanating from a large number of passages in side sections positioned very close to the upper and lower surface of the wafer. The gas heated by the side sections and the heated side sections themselves quickly heat the wafer to a desired temperature. Process gas directed to the “device side” of the wafer can be kept at a temperature that will not cause deposition on that side section, but yet the desired wafer temperature can be obtained by heating non-process gas from the other side section to the desired temperature. A plurality of passages around the periphery of the wafer on the non-processed side can be employed to provide purge gas flow that prevents process gas from reaching the non-processed side of the wafer and the adjacent area of that side section.

Abstract: A method 10 for making multi-layer electronic circuit boards having metallized apertures 34, 36 which may be selectively and electrically grounded or isolated from an electrical ground plane.

Abstract: Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped.

Abstract: A protective film (14) on a conductor (11d), where a contact hole (22) is to be formed, is removed in advance in a forming process of an etched-away opening (20) to expose the top portion of the corresponding conductor (11d) from the top surface of an insulating film (15), which has buried therein the conductor (11d) covered with the protective film. The etched-away opening (20) is refilled with the same kind of material as that for the insulating film (15), and then two contact holes, one (21) that opens to the semiconductor substrate (10) substantially devoid of the protective film and the other (22) that opens to the conductor (11d), are formed by simultaneous etching under substantially the same condition.

Abstract: A method for growing bulk GaN and AlGaN single crystal boules, preferably using a modified HVPE process, is provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth to achieve n-, i-, or p-type conductivity. In order to have growth cycles of sufficient duration, preferably an extended Ga source is used in which a portion of the Ga source is maintained at a relatively high temperature while most of the Ga source is maintained at a temperature close to, and just above, the melting temperature of Ga. To grow large boules of AlGaN, preferably multiple Al sources are used, the Al sources being sequentially activated to avoid Al source depletion and excessive degradation.

Abstract: The invention provides a method for making thin film metal oxide actuator device. According to the method a first conductive layer is deposited on a silicon substrate. Next a thin film metal oxide layer is deposited on the first conductive layer. A negative photoresist material is applied to the metal oxide layer to provide a photoresist layer. The photoresist layer is patterned using light radiation energy and developed to provide one or more exposed portions of the metal oxide layer. The photoresist layer is etched with a reactive ion plasma sufficient to remove the photoresist layer and the metal oxide layer under the photoresist layer from the first conductive layer leaving the one or more exposed portions of metal oxide layer on the first conductive layer. A second conductive layer is attached to the metal oxide layer to provide a thin film metal oxide actuator device.

Abstract: The invention is a method of introducing porous membranes into MEMS elements by supporting the membranes by frames to form an heterostructure. This is achieved by attaching to a structured or porous substrate one or more monolithically fabricated frames and membranes. Having membranes disposed on frames enables them to be batch processed and facilitates separation, handling and mounting within MEMS or nanofluidic systems. Applications include, but are not limited to, filters for gases or liquids, electron transmissive windows and scanning electron microscopy (SEM) accessible arrays of nanotest tubes containing liquid phases and other sample states. The invention includes the apparatus made by the method.