Patents Examined by Benjamin Sandvik
  • Patent number: 10153326
    Abstract: According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, a first insulating layer and a first layer. The first conductive layer includes a first metal capable of forming a compound with silicon. The second conductive layer includes at least one selected from a group consisting of tungsten, molybdenum, platinum, tungsten nitride, molybdenum nitride, and titanium nitride. The first insulating layer is provided between the first conductive layer and the second conductive layer. The first layer is provided between the first insulating layer and the second conductive layer. The first layer includes silicon.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: December 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masato Koyama, Harumi Seki, Shosuke Fujii, Hidenori Miyagawa
  • Patent number: 10150667
    Abstract: Conventional package for integration of MEMS and electronics suffer from profiles that are undesirably high to due to the thickness of the glass. Also in conventional package manufacturing, the MEMS and electronic devices are first individualized, and the individualized MEMS and electronics are combined into a package, and thus can be costly. To address these and other disadvantages, a panel level packaging is proposed. In this proposal, plural MEMS devices are integrated with plural semiconductor devices at a panel level, and the panel is then individualized into separate packages.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: December 11, 2018
    Assignee: OBSIDIAN SENSORS, INC.
    Inventors: Yaoling Pan, Omar Bchir
  • Patent number: 10153229
    Abstract: A method for use in manufacturing semiconductor devices such as, e.g., semiconductor power devices includes providing: a semiconductor die provided with bonding pads, a lead frame for the semiconductor die, a wire bonding layout including electrically conductive wires coupling bonding pads of the semiconductor die with leads in the lead frame. One or more bonding pads of the semiconductor die is/are coupled to a respective lead in the lead frame via a plurality of wires with a plurality of mutually insulated testing lands in the respective lead, so that the plurality of wires are coupled to respective testing lands. The electrical connection between such a bonding pad and the respective lead may be tested by testing the individual electrical connections between the bonding pad and the plurality of testing lands.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: December 11, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10147757
    Abstract: Methods and systems for integrating image sensor structures with collimator filters, including manufacturing methods and associated structures for forming collimator filters at the wafer level for integration with image sensor semiconductor wafers. Methods of making an optical biometric sensor include forming a collimator filter layer on an image sensor wafer, wherein a plurality of light collimating apertures in the collimator filter layer are aligned with a plurality of light sensing elements in the image sensor wafer, and after forming the collimator filter layer on the image sensor wafer, singulating the image sensor wafer into a plurality of individual optical sensors.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: December 4, 2018
    Assignee: Synaptics Incorporated
    Inventors: Young Seen Lee, Paul Wickboldt, Patrick Smith, Robert John Gove, Jason Goodelle
  • Patent number: 10141231
    Abstract: A method includes forming two fins extending from a substrate, each fin having two source/drain (S/D) regions and a channel region; forming a gate stack engaging each fin at the respective channel region; depositing one or more dielectric layers over top and sidewall surfaces of the gate stack and over top and sidewall surfaces of the S/D regions of the fins; and performing an etching process to the one or more dielectric layers. The etching process simultaneously produces a polymer layer over the top surface of the gate stack, resulting in the top and sidewall surfaces of the S/D regions of the fins being exposed and a majority of the sidewall surface of the gate stack still being covered by the one or more dielectric layers. The method further includes growing one or more epitaxial layers over the top and sidewall surfaces of the S/D regions of the fins.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yu Yang, Chia-Ta Yu, Kai-Hsuan Lee, Sai-Hooi Yeong, Feng-Cheng Yang
  • Patent number: 10134886
    Abstract: In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: November 20, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • Patent number: 10134604
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Patent number: 10134926
    Abstract: A time-of-flight detector includes a semiconductor layer and a light modulation structure. The semiconductor layer is configured to translate light radiation into electrical charge. The light modulation structure is configured to increase a path of interaction of light radiation through the semiconductor layer. In some example implementations, the light modulation structure is configured to deflect at least some light radiation at an increased angle through the semiconductor layer. In some example implementations, the light modulation structure is configured to reflect light radiation more than once through the semiconductor layer.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: November 20, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Onur Can Akkaya, Satyadev Nagaraja, Tamer Elkhatib, Cyrus Bamji, Swati Mehta
  • Patent number: 10132853
    Abstract: The embodiments herein are directed to monitoring in real time, power system data so as to provide insights into global operation of a power grid. Such a scheme disclosed herein utilizes rules, which are created by analyzing PMU measurement data, in order to detect the fault location (bus and line) and fault type. Three common types of faults in a power grid, single-line-to-ground (SLG), line-to-line (LL), and three phase faults, can be detected using the methods herein.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: November 20, 2018
    Assignee: WASHINGTON STATE UNIVERSITY
    Inventors: Xiaodong Liang, Scott Andrew Wallace, Xinghui Zhao
  • Patent number: 10128403
    Abstract: A method of manufacturing a semiconductor substrate including forming a first layer on a substrate, patterning the first layer to form a plurality of patterns spaced apart from one another, forming a second layer on the patterns to cover each of the patterns, heat-treating the second layer to form cavities in the patterns between the second layer and the substrate, and growing the second layer covering the cavities.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: November 13, 2018
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Shiro Sakai
  • Patent number: 10128254
    Abstract: A semiconductor device includes a substrate, a first pattern, a first gate electrode, and a second pattern. The first pattern is disposed on the substrate and extends in a first direction substantially vertical to an upper surface of the substrate, and includes a first part, a second part and a third part sequentially disposed on the substrate. The first gate electrode is connected to the second part and extends in a second direction different from the first direction. The second pattern is disposed on the substrate, extends in the first direction, is connected to the first part, and does not contact the first gate electrode.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Jin Kwon, Kang-Ill Seo
  • Patent number: 10109713
    Abstract: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 23, 2018
    Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, CREE INC.
    Inventors: Alessandro Chini, Umesh Kumar Mishra, Primit Parikh, Yifeng Wu
  • Patent number: 10103186
    Abstract: A photoelectric conversion section contains a semiconductor element having a laminated structure which contains an electroconductor, a semiconductor, and an insulator provided between the electroconductor and the semiconductor, in which the insulator is a silicon oxide film containing nitrogen in a main portion located between the electroconductor and the semiconductor.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 16, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Katsunori Hirota
  • Patent number: 10103207
    Abstract: The present disclosure relates to a display device in the field of display.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: October 16, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Wang, Yafeng Yang, Xiaochuan Chen, Jing Lv, Jifeng Tan, Can Zhang
  • Patent number: 10103083
    Abstract: A semiconductor structure comprises one or more semiconductor devices, each of the semiconductor devices having two or more electrical connections; one or more first conductors connected to a first electrical connection on the semiconductor device, the first conductor comprising a first material having a positive Seebeck coefficient; and one or more second conductors connected to a second electrical connection on the semiconductor device, the second conductor comprising a second material having a negative Seebeck coefficient. The first conductor and the second conductor conduct electrical current through the semiconductor device and conduct heat away from the semiconductor device.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 16, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Siyuranga O. Koswatta, Sungjae Lee, Lan Luo, Scott K. Springer, Richard A. Wachnik
  • Patent number: 10096772
    Abstract: Embodiments of the present invention describe a method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising depositing a poly-silicon layer on a substrate depositing a carbon layer above the poly-silicon layer, patterning a photo-resist layer on the carbon layer, depositing a first spacer layer on the photo-resist layer and performing a modified photolithography process on the photo resist layer after etching back the spacer layer creating sidewalls.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: October 9, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Jun Okuno
  • Patent number: 10096712
    Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The method includes the steps of: forming a plurality of fins supported by a substrate; depositing a gate layer on the fins; and etching the gate layer by plasma etching with an etching gas to form a gate having two notch features. The etching gas is supplied at a ratio of a flow rate at a center area of the substrate to a flow rate at a periphery area of the substrate in a range from 0.2 to 1. The disclosure also provides a method of monitoring a quality of the FinFET device, the method comprising: measuring a profile of the notch feature; and obtaining the quality of the FinFET device by comparing the profile of the notch feature with a predetermined criterion.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10096658
    Abstract: Providing a light-emitting element emitting light in a broad emission spectrum. A combination of a first organic compound and a second organic compound forms an exciplex. The first organic compound has a function of converting triplet-excitation energy into light emission. The lowest triplet excitation level of the second organic compound is higher than or equal to the lowest triplet excitation level of the first organic compound, and the lowest triplet excitation level of the first organic compound is higher than or equal to the lowest triplet excitation level of the exciplex. Light emission from a light-emitting layer includes light emission from the first organic compound and light emission from the exciplex.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: October 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeyoshi Watabe, Satomi Mitsumori, Nobuharu Ohsawa, Harue Osaka, Kunihiko Suzuki, Satoshi Seo
  • Patent number: 10090203
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: October 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10090461
    Abstract: Oxide-based three-terminal resistive switching logic devices and methods of fabricating oxide-based three-terminal resistive switching logic devices are described. In a first example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes an active oxide material region disposed directly between a metal source region and a metal drain region. The device also includes a gate electrode disposed above the active oxide material region. In a second example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes a first active oxide material region spaced apart from a second oxide material region. The device also includes metal input regions disposed on either side of the first and second active oxide material regions. A metal output region is disposed between the first and second active oxide material regions.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Prashant Majhi, Ravi Pillarisetty, Brian S. Doyle, Niloy Mukherjee, Uday Shah, Robert S. Chau