Abstract: Embodiments of the disclosed subject matter provide a device including an active-matrix driven flexible display including a plurality of Organic Light Emitting Diodes (OLEDs) formed on a plastic substrate, where each OLED includes a phosphorescent first emissive layer, where the display operates at a luminance value of at least 500 cd/m2 with a luminance decay of not more than about 3% after 10,000 hours of operation, and where the display is formed on the plastic substrate having a glass transition temperature of the less than 200° C.

Abstract: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.

Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

Abstract: Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

Abstract: Embodiments of a light emitting device and a method for fabricating the same are provided. The light emitting device comprises a cavity and one or more light emitting elements. The cavity is formed to a depth of 450 ?m or less, and the light emitting elements are installed in the cavity. A fabricating method includes forming a package body having a cavity with a depth of 250 ?m to 450 ?m and at least one lead frame disposed at the bottom surface of the cavity, mounting at least one light emitting element on the lead frame, and molding a molding member in the cavity.

Abstract: A semiconductor wafer with (100) plane orientation has two orthogonal cleavage directions. A notch is provided so as to indicate one of these directions. During irradiation with a flash, the semiconductor wafer warps about one of two radii at an angle of 45 degrees with respect to the cleavage directions such that the upper surface thereof becomes convex, and the opposite ends of the other radii become the lowest position. Eight support pins in total are provided in upright position on the upper surface of a holding plate of a susceptor while being spaced at intervals of 45 degrees along the same circumference. The semiconductor wafer is placed on the susceptor such that any of the support pins supports a radius at an angle of 45 degrees with respect to a cleavage direction.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors are described. The memory cell includes a substrate having a non-volatile memory (NVM) region and a plurality of metal-oxide-semiconductor (MOS) regions. A NVM transistor in the NVM region includes a tunnel dielectric on the substrate, a charge-trapping layer on the tunnel dielectric, and a blocking dielectric comprising a high-k dielectric material over the charge-trapping layer. The plurality of MOS regions include a number of MOS transistors. At least one of the MOS transistors includes a gate dielectric comprising a high-k dielectric material over a surface of the substrate. Generally, the blocking dielectric and the gate dielectric comprise the same high-k dielectric material. Other embodiments are also described.

Abstract: An organic light emitting display device and a method of manufacturing the same are proposed. The organic light emitting display device includes: a first film formed of an organic material, and having first and second surfaces facing each other and a third surface perpendicular to the first and second surfaces; a second film formed on the first film to cover the second and third surfaces of the first film; an organic light emitting unit disposed on the second film; a third film disposed on the second film to cover the organic light emitting unit; and a fourth film disposed on the third film, formed of an organic material, and having fourth and fifth surfaces facing each other, wherein the fifth surface faces the third film.

Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.

Abstract: A gate-grounded metal oxide semiconductor (GGMOS) device is disclosed. The GGMOS is an n-type (GGNMOS) transistor used as an electrostatic discharge (ESD) protection device. The GGMOS includes a base extension region under an elevated source. The elevated source and base extension regions increase Leff and reduce beta, increasing performance of the ESD protection.

Abstract: A manufacturing method includes steps of forming a texture on a surface of a single-crystalline silicon substrate, cleaning the surface of the single-crystalline silicon substrate using ozone, depositing an intrinsic silicon-based layer on the texture on the single-crystalline silicon substrate, and depositing a conductive silicon-based layer on the intrinsic silicon-based layer, in this order. The single-crystalline silicon substrate before deposition of the intrinsic silicon-based layer has a texture size of less than 5 ?m. A recess portion of the texture has a curvature radius of less than 5 nm. After deposition of at least a part of the intrinsic silicon-based layer and before deposition of the conductive silicon-based layer, the intrinsic silicon-based layer is subjected to a plasma treatment in an atmosphere of a gas mainly composed of hydrogen.

Abstract: The present invention is directed to an MRAM device comprising a plurality of MTJ memory elements. Each of the memory elements includes a magnetic free layer and a first magnetic reference layer with an insulating tunnel junction layer interposed therebetween; a second magnetic reference layer formed adjacent to the first magnetic reference layer opposite the insulating tunnel junction layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the first magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The magnetic free layer has a variable magnetization direction substantially perpendicular to the layer plane thereof. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof.

Abstract: A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.

Abstract: A package carrier is provided. The package carrier includes a wiring layer and an insulating pattern. The wiring layer includes at least one connecting pad and at least one mounting pad. The mounting pad is used for mounting an electronic component, and the connecting pad is used for electrically connecting the electronic component. The insulating pattern is stacked on and connected to the wiring layer. A boundary surface is formed between the wiring layer and the insulating pattern. Both of the wiring layer and the insulating pattern do not extend over the boundary surface. In addition, an electronic package including the package carrier is also provided.

Abstract: The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar.

Abstract: A method for a display device is discussed. The method according to one embodiment includes forming a substrate of the display device; forming a thin film transistor on the substrate; and forming a passivation layer of a photosensitive organic material on the thin film transistor, the passivation layer having a contact hole exposing the thin film transistor. The photosensitive organic material comprises an ultraviolet absorber. The method according to the embodiment includes forming a blocking area in a mask above the contact hole; and absorbing, via the ultraviolet absorber, reflected ultraviolet (UV) rays passing by the blocking area in the mask above the contact hole.

Abstract: A light-emitting device is provided. The light-emitting device comprises: a light-emitting stack having an active layer emitting first light having a peak wavelength ? nm; and an adjusting element stacked electrically connected to the active layer in series for tuning a forward voltage of the light-emitting device; wherein the forward voltage of the light-emitting device is between (1240/0.8?) volt and (1240/0.5?) volt.

Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.

Abstract: A semiconductor device may include a first active region including a first main region and a first protruding part. The semiconductor device may include a second active region including a second main region and a second protruding part. The semiconductor device may include a first transistor formed on the first active region. The semiconductor device may include a second transistor formed on the second active region. The semiconductor device may include a connecting structure connecting the first protruding part and the second protruding part to each other.

Abstract: A chip package structure is provided. The chip package structure includes a redistribution substrate. The chip package structure includes a first chip structure over the redistribution substrate. The chip package structure includes a first solder bump arranged between and electrically connecting the redistribution substrate and the first chip structure. The chip package structure includes a first molding layer surrounding the first chip structure. The first molding layer and the first chip structure are both spaced apart from the redistribution substrate by the first solder bump, thereby defining a gap there-between. The chip package structure includes a second chip structure over the first chip structure. The chip package structure includes a second molding layer surrounding the second chip structure. The chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump, and filled into the gap.