Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a lower conductive structure, an upper conductive structure and a conductive via. The lower conductive structure includes a first dielectric layer and a first circuit layer in contact with the first dielectric layer. The upper conductive structure is attached to the lower conductive structure. The upper conductive structure includes a plurality of second dielectric layers, a plurality of second circuit layers in contact with the second dielectric layers, and defines an accommodating hole. An insulation material is disposed in the accommodating hole. The conductive via extends through the insulation material, and electrically connects the lower conductive structure.

Abstract: An apparatus for applying electromagnetic energy to an object in an energy application zone via at least one radiating element is disclosed. The apparatus may include at least one processor. The at least one processor may be configured to determine a value indicative of energy absorbable by the object at each of a plurality of frequencies and to cause the at least one radiating element to apply energy to the zone in at least a subset of the plurality of frequencies. Energy applied to the zone at each of the subset of frequencies may be a function of the absorbable energy value at each frequency.

Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.

Abstract: A LED driving system for driving a LED matrix. The LED driving system includes an interconnection structure having a first surface and a second surface opposite to the first surface and a plurality of driver dies/chips attached to the first surface of the interconnection structure. The LED matrix is divided into a plurality of sub LED matrix sections that are attached to the second surface of the interconnection structure. The interconnection structure is configured to electrically couple each one of the plurality of sub LED matrix sections to a corresponding one driver die/chip in the plurality of driver dies/chips.

Abstract: A LDMOS device includes a semiconductor layer on an insulation layer and a ring shape gate on the semiconductor layer. The ring shape gate includes a first gate portion, a second gate portion, and two third gate portions connecting the first gate portion and the second gate portion. The semiconductor device further includes a first drain region and a second drain region formed in the semiconductor layer at two sides of the ring shape gate, a plurality of source regions formed in the semiconductor layer surrounded by the ring shape gate, a plurality of body contact regions formed in the semiconductor layer and arranged between the source regions, and a first body implant region and a second body implant region formed in the semiconductor layer, respectively underlying part of the first gate portion and part of the second gate portion, and being connected by the body contact regions.

Abstract: A memory device includes an active region with a drain; a plurality of memory blocks arranged in a first direction; and a plurality of pass transistors formed in the active region and sharing the drain, each one of the plurality of pass transistors configured to transfer an operating voltage from the drain to a corresponding one of the plurality of memory blocks in response to a block select signal. The plurality of pass transistors is divided into first pass transistors and second pass transistors. A channel length direction of the first pass transistors and a channel length direction of the second pass transistors are different from each other.

Abstract: A display may include a color filter layer, a liquid crystal layer, and a thin-film transistor layer. A camera window may be formed in the display to accommodate a camera. The camera window may be formed by creating a notch in the thin-film transistor layer that extends inwardly from the edge of the thin-film transistor layer. The notch may be formed by scribing the thin-film transistor layer around the notch location and breaking away a portion of the thin-film transistor layer. A camera window may also be formed by grinding a hole in the display. The hole may penetrate partway into the thin-film transistor layer, may penetrate through the transistor layer but not into the color filter layer, or may pass through the thin-film transistor layer and partly into the color filter layer.

Abstract: A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.

Abstract: A semiconductor device includes a case enclosing a region filled with a sealing material. The case is made of resin. An electrode is fixed to the case. A section, which is a part of the electrode, is provided with a cutout that allows a part of the resin making the case to be exposed to the region.

Abstract: A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.

Abstract: A light emitting device, a method of fabricating a light emitting device and a method of controlling light emission. The light emitting device includes a plasmonic structure. The plasmonic structure is configured to have a plurality of localized surface plasmon resonances. The light emitting device also includes a broadband light emitting layer having an emission spectrum substantially overlapping wavelengths of the localized surface plasmon resonances. A spacer layer is disposed between the plasmonic structure and the broadband light emitting layer. A color of light emitted by the broadband light emitting layer is tunable by the localized surface plasmon resonances of the plasmonic structure.

Abstract: Disclosed is a semiconductor package including a base film that has a first surface and a second surface opposite to the first surface, a plurality of input/output lines on the first surface of the base film, a semiconductor chip disposed on the first surface of the base film and connected to the input/output lines and including a central portion and end portions on opposite sides of the central portion, and a heat radiation pattern on the second surface of the base film. The heat radiation pattern corresponds to the semiconductor chip and has a plurality of openings that correspond to the end portions of the semiconductor chip and that vertically overlap the end portions of the semiconductor chip.

Abstract: An organic light-emitting device having low-driving voltage, improved efficiency, and long lifespan includes: a first electrode; a second electrode facing the first electrode; a first layer between the first electrode and the second electrode, the first layer including a first compound; a second layer between the first layer and the second electrode, the second layer including a second compound; and a third layer between the second layer and the second electrode, the third layer including a third compound; wherein the first compound does not include a nitrogen-containing heterocyclic group comprising *?N—*? as a ring forming moiety, and wherein the first compound, the second compound, and the third compound each independently include at least one group selected from groups represented by Formulae A to C:

Abstract: A device includes a micro-electromechanical system (MEMS) device layer comprising a proof mass. The proof mass includes a first proof mass portion and a second proof mass portion. The first proof mass portion is configured to move in response to a stimuli. The second proof mass portion has a spring attached thereto. The device further includes a substrate disposed parallel to the MEMS device layer. The substrate comprises a bumpstop configured to limit motion of the first proof mass portion. The device includes a first electrode disposed on the substrate facing the second proof mass portion. The first electrode is configured to apply a pulling force onto the second proof mass portion and to move the second proof mass portion towards the first electrode.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a first semiconductor layer, a supporting structure, a second semiconductor layer, and a plurality of channel structures. The memory stack includes vertically interleaved conductive layers and dielectric layers and has a core array region and a staircase region in a plan view. The first semiconductor layer is above and overlaps the core array region of the memory stack. The supporting structure is above and overlaps the staircase region of the memory stack. The supporting structure and the first semiconductor layer are coplanar. The second semiconductor layer is above and in contact with the first semiconductor layer and the supporting structure. Each channel structure extends vertically through the core array region of the memory stack and the first semiconductor layer into the second semiconductor layer.

Abstract: A semiconductor device including a substrate, a first transistor and a second transistor is provided. The first transistor includes a first gate structure over the first semiconductor fin. The first gate structure includes a first high-k layer and a first work function layer sequentially disposed on the substrate, a material of the first work function layer may include metal carbide and aluminum, and a content of aluminum in the first work function layer is less than 10% atm. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer and a second work function layer sequentially disposed on the substrate. A work function of the first work function layer is greater than a work function of the second work function layer.

Abstract: Embodiments are disclosed for providing a ball grid array pattern for an integrated circuit. An example integrated circuit apparatus includes an integrated circuit and a ball grid array. The integrated circuit includes at least a package substrate and a silicon chip. The ball grid array is disposed on the package substrate of the integrated circuit. The ball grid array includes a first set of solder balls that is configured to provide electrical connections for communication channels and a second set of the solder balls associated with an electrical ground. The first set of solder balls includes a first subset of solder balls configured in a first orientation and a second subset of solder balls configured in a second orientation. Furthermore, at least one solder ball from the second set of the solder balls is disposed between the first subset of solder balls and the second subset of solder balls.

Abstract: A three-dimensional semiconductor memory device may include a cell wafer including a source plate, a plurality of first word lines stacked to be spaced apart from one another along a plurality of first vertical channels projecting from a bottom surface of the source plate in a vertical direction, and a plurality of second word lines stacked to be spaced apart from one another along a plurality of second vertical channels projecting from a top surface of the source plate in a vertical direction; a first peripheral wafer bonded to a bottom surface of the cell wafer, and including a first row decoder unit which transfers an operating voltage to the plurality of first word lines; and a second peripheral wafer bonded to a top surface of the cell wafer, and including a second row decoder unit which transfers an operating voltage to the plurality of second word lines.

Abstract: A package substrate is adapted to a ball grid array package. The substrate includes two substrate contacts, two solder ball pads, two via holes and two signal lines. A connection line of the two substrate contacts is substantially perpendicular to a connection line of the two solder ball pads. The two substrate contacts are respectively connected to the two via holes by the two signal lines. Each signal line includes a circuit trace section, an approaching section and a bifurcating section connected in sequence. The two circuit trace sections of each signal line are substantially arranged in parallel. The two approaching sections are substantially arranged in parallel and substantially symmetrical about the connection line of the solder ball pads. The two bifurcating sections are substantially symmetrical about the pad connection line and respectively electrically connected to the two via holes.

Abstract: The present invention relates to a display device and, in particular, to a display device using a semiconductor light emitting diode. A display device according to the present invention comprises a substrate having a plurality of metal pads; and a plurality of semiconductor light emitting diodes electrically connected to the metal pads through self-assembly.