Abstract: Methods, systems, and devices for wireless communications are described. An encoding device may encode a set of source symbols using one or more raptor codes to generate a first set of encoded symbols and may transmit the first set of encoded symbols to a decoding device. The decoding device may successfully recover a source symbol of the set of source symbols from the first set of encoded symbols and may transmit an indication of the source symbol to the encoding device. The encoding device may encode one or more source symbols of the set of source symbols using the one or more raptor codes to generate a second set of encoded symbols based on receiving the indication of the source symbol and may transmit the second set of encoded symbols to the decoding device.

Abstract: A processor-implemented method includes receiving a signal representing a first encoded data and calculating an estimated timing offset and/or an estimated frequency offset associated with the signal. A correction of at least one of a timing offset or a frequency offset of the signal is performed based on the estimated timing offset and/or the estimated frequency offset, to produce a modified signal. An effective channel is subsequently detected based on the signal or the modified signal. A second encoded data is generated based on the modified signal, a known vector, at least one left singular vector of the effective channel, and at least one right singular vector of the effective channel. A signal representing the second encoded data is transmitted to a communication device for identification of contents of a message at a different processor.

Abstract: A communication unit for performing soft-decision demodulation includes a receiver that receives a transmitted signal conveying a first set of bits including k bits selected from a set of 2k possible signals. A demodulator includes a bank of 2k correlators that detects a transmission of each possible transmitted signal, and outputs 2k magnitudes of correlator outputs, based on the detected possible transmitted signals, as a first set of inputs. A de-mapper circuit receives the first set of inputs and determines derived from a plurality of aggregated correlator output magnitude distributions of the first set of inputs, wherein the plurality of aggregated correlator output magnitude distributions is fewer than 22k; and calculates therefrom a first set of aposteriori soft bits including k soft bits. In this manner, high quality soft-decisions can be obtained in a robust and practical manner.

Abstract: A receiver circuit includes data lane modules, a clock lane module, a bias current controller and a link layer. Each of the data lane modules receive respective data signals. The clock lane module receives clock signals and provides each of the data lane modules with a respective divided clock signal among divided clock signals. The bias current controller controls a clock bias current. The link layer provides a bias control signal to the bias current controller and provides clock gating signals to the clock lane module, based on low power data signals and low power clock signals. The bias current controller, based on the bias control signal, provides the clock bias current having a first magnitude to the clock lane module in a second power mode and provides the clock bias current having a second magnitude to the clock lane module in a third power mode.

Abstract: A synchronization circuit, a semiconductor storage device, and a synchronization method provided herein, which are capable of performing synchronization on a small circuit scale, includes: a first delay circuit delaying a input synchronization signal by a first predetermined time to generate a first delay synchronization signal; a second delay circuit delaying the first delay synchronization signal by a second predetermined time to generate a second delay synchronization signal; a first synchronization circuit outputting a first output data generated by synchronizing the input data with the input synchronization signal; a second synchronization circuit outputting a second output data generated by synchronizing the input data with the first delay synchronization signal; and a resynchronization circuit resynchronizing the input data with the second delay synchronization signal to update the first output data to the first synchronization circuit when the first output data is inconsistent with the second output d

Abstract: A technical solution is directed to a clock recovery apparatus for multi-level signaling on a single-lane communication interface. The apparatus can use bin-map logic to successfully recover a common clock per symbol received on the multi-level signal interface. The multi-level signal can be PAM4 signaling where two bits are encoded to represent four levels. The clock recovery apparatus can detect signal level through individual edge detectors for each of the two bits and can handle jitter up to half-clock period.

Abstract: A clock data recovery circuit is provided. The clock data recovery circuit includes a charge pump circuit, a voltage controlled delay line circuit, a charge pump current generator, a phase-frequency detector and a frequency detector. The charge pump circuit generates a control voltage according to a first control signal, a second control signal and a charge pump current. The voltage controlled delay line circuit generates a data clock signal according to the control voltage and a reference clock signal. The charge pump current generator generates the charge pump current to the charge pump circuit according to the control voltage. The phase-frequency detector generates the first control signal according to a feedback clock signal and the reference clock signal. The frequency detector generates the second control signal according to the feedback clock signal and the reference clock signal.

Abstract: Methods, apparatus, and systems for reducing Peak Average Power Ratio (PAPR) in signal transmissions are described. In one example aspect, a wireless communication method includes determining, for an input sequence, an output sequence. The output sequence corresponds to an output of a convolutional modulation between a set of coefficients and an intermediate sequence. The intermediate sequence is generated by inserting N zero coefficients between coefficients of the input sequence. The number of non-zero coefficients in the set of coefficients is based on N, N being a positive integer. Values of the non-zero coefficients correspond to values between 0 to ?/2 to reduce a peak to average power ratio of the output sequence. The method also includes generating a waveform using the output sequence.

Abstract: A method includes obtaining an in-phase (I) input signal and a quadrature (Q) input signal at a quadrature modulator. The method also includes performing constant envelope bi-phase shift keying (CE-BPSK) modulation using the quadrature modulator to generate a modulated output signal. The modulated output signal includes a CE-BPSK modulated waveform containing phase reversals, and the CE-BPSK modulated waveform has a substantially-constant amplitude during the phase reversals.

Abstract: A UWB pulse emitter includes an H-bridge having first and second branches in parallel, a first end common to the branches being connected to a first amplitude control module to regulate a high voltage, a second end common to the branches being connected to a second amplitude control module to regulate a low voltage. A first envelope control module controls the shape of the positive portion of a UWB pulse and a second envelope control module controls the shape of the negative portion of this pulse. Each branch comprises first and second switches for respectively switching the high voltage to a first or second input of the first envelope control module and the low voltage to a first or second output of the second envelope control module. Centre taps of the branches, between which the UWB antenna is connected, connect the outputs and the inputs of the control modules.

Abstract: A method for demodulating an RF signal to polar in-phase and quadrature (IQ) components that includes converting an RF signal with an analog-to-digital converter and calculating the polar in-phase and quadrature (IQ) components of the RF signal as an IQ phasor phase angle and an IQ amplitude using a digital processor. The analog-to-digital converter uses a sampling rate, where, when the sampling rate used has sampling rates other than 3 times an RF carrier frequency of the RF signal, a digital logic circuit splines data to the sampling rate of 3 times the RF carrier frequency of the RF signal. The digital processor calculates the polar in-phase and quadrature (IQ) components of the RF signal as an IQ phasor phase angle and an IQ amplitude using addition, subtraction, multiplication, division, and absolute value.

Abstract: A data transfer circuit according to the invention includes a memory configured to write data in accordance with a write pointer in synchronization with a first clock, and read out the data in accordance with a readout pointer in synchronization with a second clock, a clock generation circuit configured to generate the second clock by multiplying a reference clock by a rational number N, a frequency error estimation circuit configured to estimate a frequency error between the first clock and the second clock based on a change amount of a pointer difference between the write pointer and the readout pointer, and an adjustment circuit configured to output, as an adjustment multiple ?N, a value obtained by dividing the estimated frequency error by a frequency of the reference clock. The clock generation circuit generates the second clock by multiplying the reference clock by a rational number (N+?N).

Abstract: Architectures for inter-converting bitstreams and symbol streams of PAM and/or QAM constellations of different sizes that are not base-2 integers. Some of such constellations may be Gray-coded, and the constellation mapping may be performed to achieve an equiprobable distribution of different constellation symbols. Some embodiments may be compatible with FEC schemes. In an example embodiment, a transmitter DSP may employ a conventional constellation mapper preceded by an electronic encoder programmed to exclude some constellation-symbol labels from the bitstream applied to the mapper. In different embodiments, the electronic encoder may employ a CCDM and/or a long-division operation to select some amplitudes of the constellation and to exclude others. At least some embodiments are beneficially capable of achieving a smaller gap to the Shannon limit than comparable conventional solutions.

Abstract: Methods and apparatuses for codebook based UL transmission are provided. A method for operating a UE comprises transmitting a UE capability information about a UL codebook for 8 antenna ports; receiving an indication indicating a TPMI for a transmission of a PUSCH; and transmitting the PUSCH based on the indicated TPMI, wherein the TPMI indicates a precoding matrix from the UL codebook for the 8 antenna ports, the UL codebook includes full-coherent (FC) precoding matrices comprising all non-zero entries, and an l-th column of a FC precoding matrix is associated with an l-th layer of the PUSCH transmission.

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

Abstract: A terminal determines a target code rate by using a reference code rate, which is based on a modulation scheme and a modulation order, and an adjustment coefficient ? that lowers the reference code rate. The terminal transmits/receives a signal encoded based on the target code rate.

Abstract: A radio frequency (RF) communication assembly includes an RF communication circuit and a compensator apparatus. The compensator apparatus receives an input including an I-component of a pre-compensated signal, a Q-component of the pre-compensated signal, and encoded operating conditions of the RF communication circuit. The RF communication circuit includes RF circuit components causing signal impairments. The compensator apparatus perform neural network computing on the input, and the RF communication assembly generates a compensated output signal that compensates for at least a portion of the signal impairments.

Abstract: A method performed by a network node for handling a Single User (SU) Multiple Input Multiple Output (MIMO) transmission from a User Equipment (UE) in a wireless communications network is provided. The network node selects an allowed precoding matrix set for the SU MIMO transmission. The network node further estimates a raw covariance matrix for the SU MIMO transmission, based on a Demodulation Reference Signal, DMRS, of a Physical Uplink Shared Channel, PUSCH, received from the UE. The network node then selects a precoding matrix and a rank for the SU MIMO transmission, based on the estimated raw covariance matrix and the selected allowed precoding matrix set.

Abstract: A PLC network system and method operative with OFDM for generating MIMO frames with suitable preamble portions configured to provide backward compatibility with legacy PLC devices and facilitate different receiver tasks such as frame detection and symbol timing, channel estimation and automatic gain control (AGC), including robust preamble detection in the presence of impulsive noise and frequency-selective channels of the PLC network. A PLC device may include a delayed correlation detector and a cross-correlation detector operating in concert to facilitate preamble detection in one implementation.

Abstract: The present disclosure provides a decision feedback equalizer circuit. The decision feedback equalizer circuit includes: a first adder circuit, configured to add sampled data, first correction data and target correction data; a first sampler amplifier, configured to sample data output by the first adder circuit through a first signal component in a first clock signal to obtain a first sampling result; a second adder circuit, configured to add the sampled data, the first correction data and the target correction data; a second sampler amplifier, configured to sample data output by the second adder circuit through a second signal component in the first clock signal to obtain a second sampling result; and a correction parameter processing element, configured to determine the target correction data through a second clock signal, the first sampling result and the second sampling result.