Patents Examined by Binh C. Tat
  • Patent number: 12126195
    Abstract: A method of reducing a power consumption of a wireless device according to one embodiment includes performing, by the wireless device, a calibration of wireless communication circuitry of the wireless device in response to establishing a wireless communication connection with a wireless access point, determining, by the wireless device, a number of disconnections between the wireless device and the wireless access point over a predefined period of time, and increasing, by the wireless device, a sleep interval of the wireless communication circuitry of the wireless device in response to determining the number of disconnections between the wireless device and the wireless access point over the predefined period of time is less than a threshold number of disconnections.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: October 22, 2024
    Assignee: Schlage Lock Company LLC
    Inventors: Liqiang Du, David I. Newby, Ilamparithi Ashok Dileephan
  • Patent number: 12126185
    Abstract: Systems, methods and apparatus for wireless charging are disclosed. A charging device has a plurality of charging cells provided on a charging surface, a charging circuit and a controller. The controller may be configured to cause the charging circuit to send pings from a plurality of charging coils using an analog ping process to scan for one or more ping responses from a receiving device in proximity to the charging surface. A subset of charging coils of the plurality of charging coils that received ping responses from the receiving device in response to the sending of pings with the analog process may be determined. Subsequently, the controller then sends pings from the subset of charging coils using a digital ping process. A combination of one or more charging coils of the subset of charging coils may then be selected based on ping responses from the receiving device.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: October 22, 2024
    Assignee: Aira, Inc.
    Inventors: Eric Heindel Goodchild, David Russell
  • Patent number: 12124784
    Abstract: A method of producing inductive sensors, including LVDTs and inductive encoders, manufactured by plotting fine wire onto a planar substrate. A sensor is constructed using a computer-controlled machine to place wire onto a planar adhesive substrate. This substrate forms a predictable and uniform surface to deposit each turn of wire, and so the placement accuracy is considerably better than conventional coil winding. This planar substrate can then be manipulated into a desired three-dimensional shape (e.g., by folding, rolling, corrugating, winding, etc.), carrying the wire along with it. In particular, the same CNC machine used to place the wire can be used to cut, crease, score, or otherwise pattern the substrate to facilitate the three-dimensional arrangement.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: October 22, 2024
    Assignee: Massachusetts Institute of Technology
    Inventors: Samuel E. Calisch, Neil A. Gershenfeld
  • Patent number: 12112116
    Abstract: A system and a method of optimizing an optical proximity correction (OPC) model for a mask pattern of a photo mask is disclosed. A machine learning (ML) based model builder includes an OPC model, measurement data and a random term generator. Random terms are generated in a M-dimensional space by the random term generator. The ML based model builder classifies the random terms to clusters by applying a classifying rule. A representative subset of the random terms is determined among the classified clusters, and the representative subset is added to the OPC model.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zhiru Yu, Lin Zhang, Danping Peng, Junjiang Lei
  • Patent number: 12101885
    Abstract: A server motherboard includes a protective film, a substrate, and a power supply circuit. An equivalent electrical parameter of the protective film changes as a shape of the protective film changes. The shape changes when a temperature of the server mother board is greater than a predetermined temperature. A portion of at least one side surface of the substrate is covered by the protective film. The power supply circuit is electrically connected to the protective film and configured to detect the equivalent electrical parameter of the protective film. The power supply circuit stops outputting a power supply voltage to the substrate when a change of the equivalent electrical parameter is detected.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: September 24, 2024
    Assignee: LENOVO (BEIJING) LIMITED
    Inventor: Yongbin Hu
  • Patent number: 12093632
    Abstract: A method for calibrating a process model and training an inverse process model of a patterning process. The training method includes obtaining a first patterning device pattern from simulation of an inverse lithographic process that predicts a patterning device pattern based on a wafer target layout, receiving wafer data corresponding to a wafer exposed using the first patterning device pattern, and training an inverse process model configured to predict a second patterning device pattern using the wafer data related to the exposed wafer and the first patterning device pattern.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: September 17, 2024
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Marinus Aart Van Den Brink, Yu Cao, Yi Zou
  • Patent number: 12090886
    Abstract: A method for predictive charging control for an electrical energy store of a motor vehicle, wherein an energy exchange between the energy store and an electrical energy source is controlled by a charging device. This provides that a future time profile of a non-energy requirement resulting from a respective parking phase of the motor vehicle is predicted and, independently of an availability of a charging power of the energy source, a state of charge of the energy store is kept below a limit value by the charging device if the predicted time profile of the non-energy requirement satisfies a predetermined rest criterion for a predetermined next time interval.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: September 17, 2024
    Assignee: Vitesco Technologies GmbH
    Inventor: Stefan Grubwinkler
  • Patent number: 12086685
    Abstract: Methods, systems and apparatus for error correction of fermionic quantum simulation. In one aspect, a method includes representing a fermionic system as a graph of vertices and edges, where each vertex represents a fermionic system fermionic mode and each edge represents an interaction between two respective fermionic modes; allocating a qubit to each edge in the graph to form a qubit system; determining qubit operators that satisfy a set of fermionic commutation and dependence relations, where the qubit operators are non-uniform with respect to the graph vertices; determining stabilizer operators corresponding to products of quadratic Majorana operators on respective loops in the graph, where a common eigenspace of the defined stabilizer operators defines a code subspace that encodes states of the fermionic system to be simulated; and simulating the fermionic system by evolving the qubit system under a qubit Hamiltonian that includes the determined qubit operators and stabilizer operators.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 10, 2024
    Assignee: Google LLC
    Inventors: Zhang Jiang, Ryan Babbush, Jarrod Ryan McClean
  • Patent number: 12086522
    Abstract: For a method of manufacturing a semiconductor device, a corresponding layout diagram is stored on a non-transitory computer-readable medium, the layout diagram being arranged relative to first and second perpendicular directions, the layout diagram including cells such that, for a subset of the cells, each subject one of the cells (subject cell) in the subset has a neighborhood including first and second neighbor cells on corresponding first and second sides of the subject cell relative to the first direction. The method includes: for each subject cell in the subset, generating a sidefile which represents neighborhood-specific proximity-effect information.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Pin Chen, Florentin Dartu, Wei-Chih Hsieh, Tzu-Hen Lin, Chung-Hsing Wang
  • Patent number: 12085619
    Abstract: The present disclosure relates to a method for estimating a state of charge (SOC) of a battery and a battery management system applying the same. A method for estimating a SOC of a battery in a method for estimating a SOC of a battery module assembly including battery modules respectively including a plurality of battery cells includes: receiving a battery current from a current sensor; comparing the battery current and a threshold current, and selecting a method for estimating a first SOC or a method for estimating a second SOC according to a comparison result; estimating a SOC of the cells according to the selected method for estimating a state of charge; and estimating the SOC of the battery module assembly by combining the estimated SOC of the battery cells.
    Type: Grant
    Filed: September 5, 2020
    Date of Patent: September 10, 2024
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventor: Yong Chul Sung
  • Patent number: 12079557
    Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: September 3, 2024
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Mark McDermott, Jaydeep Kulkarni
  • Patent number: 12074217
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: August 27, 2024
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Patent number: 12061952
    Abstract: Using a model executing on a classical processor, a set of classical features is scored. The scored set of classical features is divided into a set of feature groups, a number of classical features in a group determined according to a qubit capability of a quantum processor. Using a model executing on the quantum processor and a group of the scored set of classical features, a set of quantum features is scored. The score of a quantum feature is adjusted according to an accuracy of the quantum data model. The scored set of classical features and the scored set of quantum features are combined according to a measure of differences between the scored set of classical features and the scored set of quantum features. Using the combined set of scored features and a first set of input data of a resource, a valuation of a resource is calculated.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: August 13, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aaron K. Baughman, Gururaja Hebbar, Micah Forster, Kavitha Hassan Yogaraj, Yoshika Chhabra
  • Patent number: 12061241
    Abstract: A rechargeable battery short-circuit early detection device that detects a short-circuit in a rechargeable battery includes one or more processors connected to a current sensor that detects a charging current of the rechargeable battery, wherein the one or more processors are programmed to: if a detected temporal slope of the charging current exceeds a first threshold, determine that there is a possibility that a short circuit has occurred in at least one of the cells; detect anew a temporal slope of the charging current after a prescribed period of time has elapsed since the determination of said possibility; and thereafter, if the anew detected temporal slope of the charging current exceeds a second threshold that is greater than the first threshold, determine that there is a possibility that the short-circuit is progressing, and output a signal indicating said possibility.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: August 13, 2024
    Assignees: FURUKAWA ELECTRIC CO., LTD., FURUKAWA AUTOMOTIVE SYSTEMS INC.
    Inventors: Naotaka Uchino, Etsuzo Sato
  • Patent number: 12055904
    Abstract: A method for predicting yield relating to a process of manufacturing semiconductor devices on a substrate, the method including: obtaining a trained first model which translates modeled parameters into a yield parameter, the modeled parameters including: a) a geometrical parameter associated with one or more selected from: a geometric characteristic, dimension or position of a device element manufactured by the process and b) a trained free parameter; obtaining process parameter data including data regarding a process parameter characterizing the process; converting the process parameter data into values of the geometrical parameter; and predicting the yield parameter using the trained first model and the values of the geometrical parameter.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 6, 2024
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Youping Zhang, Boris Menchtchikov, Cyrus Emil Tabery, Yi Zou, Chenxi Lin, Yana Cheng, Simon Philip Spencer Hastings, Maxime Philippe Frederic Genin
  • Patent number: 12049145
    Abstract: A charging assembly is for charging an electric vehicle. The charging assembly has an electrical socket configured for connecting a charging station to a specific branch an electric vehicle supply installation. The installation has a fuse cabinet and a branch connected to the fuse cabinet. The socket has a data storage medium readable by the charging station. The data storage medium has a data field representing a maximum electrical current that can be drawn from the fuse cabinet by the specific branch, and optionally a data field representing a maximum electrical current that can be drawn by the charging station. The charging station can be coupled to the electrical socket, and is configured for reading the data storage medium including the data fields and for accordingly adapting the way current is drawn from the branch and provided to the electric vehicle.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: July 30, 2024
    Assignee: Easee AS
    Inventors: Kjetil Næsje, Jonas Helmikstøl, Steffen Mølgaard, Ola Stengel
  • Patent number: 12045554
    Abstract: Embodiments of the present application provide a circuit simulation method and a device. The method includes: determining a top-layer structure and a minimum circuit cell layer of a circuit schematics; determining, in a circuit layout, an area and a relative distribution location of each target circuit cell in the minimum circuit cell layer; generating a first circuit structure based on the top-layer structure, each target circuit cell, and the area and the relative distribution location of each target circuit cell in the circuit layout; and adding a parasitic effect circuit to the first circuit structure, generating a target circuit structure corresponding to the circuit schematics, and performing simulation based on the target circuit structure.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: July 23, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Fan Xu
  • Patent number: 12046724
    Abstract: The present invention provides a method for reasonably adjusting an end-of-discharge voltage of a lithium battery with attenuation of a battery life. The method includes: acquiring an end-of-charge voltage, an end-of-discharge voltage and a rated capacity based on a basic parameter table for a lithium battery, then setting a safety end-of-charge voltage and a safety end-of-discharge voltage to obtain an initial safety discharge capacity, and finally setting a preset discharge capacity of the battery; using an Ampere-hour integration method to estimate a discharged power, taking the preset discharge capacity as a discharge standard, and stopping discharge when the discharged power reaches the preset discharge capacity; and the safety discharge capacity being gradually less than the preset discharge capacity within a battery life cycle, and the battery stopping discharge when the voltage reaches the safety end-of-discharge voltage.
    Type: Grant
    Filed: May 9, 2020
    Date of Patent: July 23, 2024
    Assignee: UNIVERSITY OF SHANGHAI FOR SCIENCE AND TECHNOLOGY
    Inventors: Yuejiu Zheng, Zheng Meng, Yong Zhou, Xin Lai, Long Zhou, Anqi Shen, Wenkuan Zhu, Yunfeng Huang, Haidong Liu
  • Patent number: 12039249
    Abstract: A system and method for fixing DRC violations includes receiving a layout pattern having a design rule check (DRC) violation therein, determining that the layout pattern is an inlier based upon a comparison of the layout pattern with a plurality of previously analyzed layout patterns. The comparison may be performed by an anomaly detection algorithm. The system and method may also include selecting a recipe from a pool of recipes previously applied to the plurality of previously analyzed layout patterns for fixing the DRC violation in the layout clip upon determining that the layout pattern is an inlier.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Chen Huang, Heng-Yi Lin, Yi-Lin Chuang
  • Patent number: 12039251
    Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first width of at least one first metal interconnect is different from a second width of one of the plurality of second metal interconnects.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lin Chuang, Huang-Yu Chen, Yun-Han Lee