Patents Examined by Binh C. Tat
  • Patent number: 10804793
    Abstract: A power factor corrector (PFC), such as for an on-board charger (OBC) for charging a vehicle traction battery, uses an input voltage and an input current from a power source to output a desired voltage. The PFC has an inductor and first and second power switches. A micro-controller generates, for each half-cycle of the input voltage, first and second reference signals respectively indicative of (i) a sinusoidal envelope of the inductor current for which the PFC will absorb sufficient power from the power source for the PFC to output the desired voltage and (ii) a reverse value of the inductor current for which zero voltage switching (ZVS) of the switches is ensured. A comparator assembly turns the first switch off (on) and the second switch on (off) upon the inductor current equaling the outer sinusoidal amplitude envelope (the reverse value) whereby the PFC outputs the desired voltage with ZVS.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: October 13, 2020
    Assignee: Lear Corporation
    Inventors: Antonio Leon Masich, Rafael Jimenez Pino, Oscar Lucia Gil, Hector Sarnago Andia, Alejandro Naval Palleres
  • Patent number: 10804724
    Abstract: A cart to store a plurality of mobile computing devices includes a plurality of slots defined by opposed plates. Each of the slots is configured to accept a corresponding mobile computing device. A first slot is defined by first and second plates, and a second slot is defined by the second plate and a third plate. The second plate includes a first transmit coil for wirelessly transmitting power to a first receive coil in a first mobile computing device within the first slot, and to a second receive coil in a second mobile computing device within the second slot.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: October 13, 2020
    Assignee: Dell Products, L.P.
    Inventors: Jace W. Files, Vinh Xuan Bui
  • Patent number: 10797505
    Abstract: A wireless charging guide system includes a wireless charging cradle, an electronic device and a visual guide medium. The electronic device includes a power storage unit and a charging unit. When the visual guide medium guides the electronic device to be placed at a first position on the top surface of the wireless charging cradle, the charging unit, with respect to the wireless charging cradle, has a charging rate larger than a first default value and starts to charge the power storage unit, wherein the visual guide medium is accessed from a remote server according to the model of the electronic device.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: October 6, 2020
    Assignees: Qisda (Suzhou) Co., Ltd., Qisda Corporation
    Inventors: Min-Jye Chen, Min-An Kuo
  • Patent number: 10789400
    Abstract: A computer-implemented method obtains data describing a plurality of synthesis scenarios associated with a very-large-scale integration design (VLSI), wherein each synthesis scenario describes a different combination of tunable design parameters for a macro of the VLSI design, and wherein the VLSI design includes a plurality of macros being tuned. The plurality of macros is ranked based on the data. The ranking produces a macro waiting list that identifies those of the synthesis scenarios that are associated with each of the macros. A subset of the synthesis scenarios is pushed from the macro waiting list to a job submission queue that is separate from the macro waiting list. The job submission queue ranks the subset of synthesis scenarios in an order in which they are to be synthesized by a synthesis tuning system. At least one synthesis scenario is submitted to the synthesis tuning system according to the order.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hung-Yi Liu, Matthew M. Ziegler
  • Patent number: 10789408
    Abstract: Systems and methods for generating coloring constraints for layout design data. A method includes receiving or determining a constraint rule, by a computer system, for a constraint between geometric elements in the layout design data. The method includes generating constraints according to the one or more constraint rules. The method includes creating one or more groups according to the generated constraints. The method includes storing the generated constraints and the one or more groups in a design layout database. Also systems and methods for identifying elements in a design layout having multiple levels of hierarchical cells.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 29, 2020
    Assignee: Mentor Graphics Corporation
    Inventor: Fedor G. Pikus
  • Patent number: 10783293
    Abstract: A checking method for checking whether a signal in a chip is interference-free, and the checking method includes the following operations: analyzing, by a processor, a netlist file to acquire a first node for outputting the signal in the chip, in which the netlist file is configured to describe a circuit architecture of the chip; searching, by the processor, candidate nodes associated with the signal according to the netlist file and the first node; and determining, by the processor, whether a first candidate node of the candidate nodes is connected to an anti-interference circuit, in order to check whether the signal is interference-free.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: September 22, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shu-Yi Kao, Yu-Lan Lo, Meng-Jung Lee, Yun-Jing Lin
  • Patent number: 10784725
    Abstract: For misalignment measurement, a method receives a plurality of position detection signals from a corresponding plurality of detection coils. The plurality of position detection signals are generated from mutual inductance between the plurality of detection coils and an energized field-generating detection coil. The method further generates detection information from the position detection signals. In addition the method calculates a lateral misalignment along a lateral Y axis from the detection information. The lateral misalignment includes a lateral misalignment distance and a lateral misalignment direction. The method calculates a vehicle speed along a longitudinal X axis from the detection information. In addition, the method energizes a transmitter power coil and controls the power transfer based on the vehicle speed and lateral misalignment.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 22, 2020
    Assignee: Utah State University
    Inventors: Zeljko Pantic, Ahmed Nasim Azad, Seyed Mohammad Reza Tavakoli
  • Patent number: 10782616
    Abstract: A method including performing a first simulation for each of a plurality of different metrology target measurement recipes using a first model, selecting a first group of metrology target measurement recipes from the plurality of metrology target measurement recipes, the first group of metrology target measurement recipes satisfying a first rule, performing a second simulation for each of the metrology target measurement recipes from the first group using a second model, and selecting a second group of metrology target measurement recipes from the first group, the second group of metrology target measurement recipes satisfying a second rule, the first model being less accurate or faster than the second model and/or the first rule being less restrictive than the second rule.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: September 22, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Daimian Wang, Shengrui Zhang, Chi-Hsiang Fan
  • Patent number: 10784703
    Abstract: A system and method is disclosed for monitoring current consumption of various subsystems and applications and adjusting functional parameters to ensure a constant current drain from the battery. The constant current drain can be dynamically adjusted based on a predetermined amount of battery life. A user can determine the amount of battery life to be required and the system adjusts current consumption of various subsystem components and applications to provide consistent and predictable battery life.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: September 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Harshal S. Chhaya, Thomas Brian Olson
  • Patent number: 10776554
    Abstract: A placed netlist is routed. A circuit is obtained that implements the placed netlist. A net in the circuit is identified to be enhanced. Space adjacent to a wire associated with the net that would accommodate a parallel wire is reserved.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: September 15, 2020
    Assignee: Avatar Integrated Systems, Inc.
    Inventors: Ping-San Tzeng, Mingsheng Han
  • Patent number: 10755008
    Abstract: A circuit comparing method includes the following operations: detecting several connection relationships between all starting points and all ending points corresponding to all starting points of a first circuit diagram; detecting several connection relationships between all starting points and all ending points corresponding to all starting points of a second circuit diagram; determining at least one difference between several connection relationships of the first circuit diagram and several connection relationships of the second circuit diagram; and outputting the at least one difference.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: August 25, 2020
    Assignee: PEGATRON CORPORATION
    Inventors: Yu-Jen Huang, Tien-Yun Kuo, Yi-Hua Chen
  • Patent number: 10746793
    Abstract: The present specification is related to analysis of digital circuits for assessing a fault sensitivity of a digital logic circuit. An example method includes: obtaining a set of input vectors that represent possible inputs to the digital logic circuit; for each output gate of the plurality of digital logic gates: (i) for each input vector of the set of input vectors, determining a cumulative output delay for the output gate, and (ii) determining an averaged cumulative output delay for the output gate by averaging the cumulative output delays for the output gate that were determined for multiple input vectors of the set of input vectors; generating a fault sensitivity score for the digital logic circuit based on the averaged cumulative output delays for the output gates of the digital logic circuit; and providing the fault sensitivity score.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: August 18, 2020
    Assignee: Accenture Global Solutions Limited
    Inventor: Nahid Farhady Ghalaty
  • Patent number: 10747922
    Abstract: A test circuit includes a plurality of codec logic elements arranged in a plurality of annular rings on an integrated circuit, each codec logic element configured to provide test bits to one or more respective scan chain and receive test result bits from the one or more respective scan chain. The test circuit further includes a decompressor logic arranged along at least one annular ring of the plurality of annular rings on the integrated circuit, the decompressor logic configured to provide test bits to at least one codec logic element in each annular ring. The test circuit also includes a compressor logic arranged transversely with respect to the plurality of annular rings on the integrated circuit, the compressor logic configured to receive test result bits from at least one of the plurality of codec logic elements.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: August 18, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Akhil Garg, Sahil Jain, Vivek Chickermane
  • Patent number: 10747931
    Abstract: Systems, apparatuses, and methods for efficiently floor planning a semiconductor chip are disclosed. Within either the processor or the memory of a computing system, each of a first block and a neighboring second block has a same height. A first metal track plan for the first block is unaligned with respect to a second metal track plan for the second block. An offset for moving each track of the second metal plan to align with a track of the first metal track plan is determined where the offset is a fraction of the height. The placement of the second block is shifted by the offset with respect to the first block. The shifted placement of the second block allows the first metal track plan for the first block to use a unidirectional pattern across the first block and the second block.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: August 18, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Keith Kasprak, Patrick W. Shaw
  • Patent number: 10740517
    Abstract: Systems and techniques are described for circuit optimization using Boolean resynthesis. Features described in this disclosure include (i) a theory of Boolean filtering, to drastically reduce the number of gates processed and still retain all possible optimization opportunities, (ii) a weaker notion of maximum set of permissible functions, which can be computed efficiently via truth tables, (iii) a parallel package for truth table computation tailored to speedup Boolean methods, (iv) a generalized refactoring engine which supports multiple representation forms and (v) a Boolean resynthesis flow, which combines these techniques.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 11, 2020
    Assignee: Synopsys, Inc.
    Inventors: Luca Gaetano Amaru, Patrick Vuillod, Jiong Luo
  • Patent number: 10740527
    Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: August 11, 2020
    Assignee: Apple Inc.
    Inventors: Farzan Farbiz, Thomas Hoffmann, Xin Yi Zhang
  • Patent number: 10734841
    Abstract: A system and method for charging a chargeable device is provided. The system can include a wireless charger including a wireless power antenna and a wireless power transmitter coupled to the wireless power antenna and configured to generate a wireless charging field in at least one charging region. The wireless charging field includes a plurality of power signals. The wireless charger further includes a communication antenna and a transceiver coupled to the communication antenna and configured to communicate with the chargeable device via the communication antenna. The wireless charger further includes a controller configured to facilitate avoidance of cross connection of the chargeable device with the wireless charger and at least one other wireless charger in which the chargeable device receives power from the wireless power transmitter of the wireless charger while communicating with at least one other wireless charger.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: William H. Von Novak, Edward Kallal
  • Patent number: 10726182
    Abstract: Disclosed approaches involve simulating a circuit design specified in a hardware description language (HDL). During simulation, a thread is started at an edge of a simulation clock signal for evaluation of states of a finite state machine (FSM) that represent a series of events specified in a statement in the HDL. The thread transitions from one state to a next state in the FSM in response to evaluation of the one state. In response to encountering a fork state in the FSM, the thread is forked into two threads during simulation. The fork state represents a composite operator in the statement, and the FSM has a branch from the fork state for each operand of the composite operator. In response to encountering a join state in the FSM by the two threads, the two threads are joined into one thread.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: July 28, 2020
    Assignee: Xilinx, Inc.
    Inventors: Sandeep S. Deshpande, Feng Cai, Saikat Bandyopadhyay
  • Patent number: 10726188
    Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 28, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kumar Chidhambara Keshavan, Ambrish Kant Varma, Taranjit Singh Kukal, Rameet Pal, Bradford Griffin, Kenneth Robert Willis, Hui Qi, Xuegang Zeng
  • Patent number: 10726186
    Abstract: A method of designing an integrated circuit includes receiving input data defining the integrated circuit, receiving information from a standard cell library including a plurality of standard cells, receiving information from a modified cell library including at least one modified cell having a same function as a corresponding standard cell among the plurality of standard cells and having a higher routability than the corresponding standard cell and generating output data by performing placement and routing in response to the input data, the information from the standard cell library and the information from the modified cell library.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Tae Kim, Jung-Ho Do, Tae-Joong Song, Doo-Hee Cho, Seung-Young Lee