Patents Examined by Binh C. Tat
  • Patent number: 11144690
    Abstract: Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of layer derivation rules implements a one-to-many mapping between the in-design layers and the derived layers. Next, a one-to-one mapping between the derived layers and process layers used in a parasitic extraction tool can be generated. Parasitic extraction on the IC design layout then be performed by providing the second IC design layout and the one-to-one mapping to the parasitic extraction tool.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 12, 2021
    Assignee: Synopsys, Inc.
    Inventors: Jun Wang, Yun-Jui Li, Bin Xu, Cheng-Ming Wu, Yu Fan Lu, Hu Cai, Yuting Fu, Hwei-Tseng Wang, Sui Zheng, Jeong-Tyng Li
  • Patent number: 11143955
    Abstract: A mask layout containing a non-Manhattan pattern is received. The received mask layout is processed. An edge of the non-Manhattan pattern is identified. A plurality of two-dimensional kernels is generated based on processed pre-selected mask layout samples. The two-dimensional kernels each have a respective rotational symmetry. The two-dimensional kernels are applied to the edge of the non-Manhattan pattern to obtain a correction field for the non-Manhattan pattern. A thin mask model is applied to the non-Manhattan pattern. The thin mask model contains a binary modeling of the non-Manhattan pattern. A near field of the non-Manhattan pattern is determined by applying the correction field to the non-Manhattan pattern having the thin mask model applied thereon. An optical model is applied to the near field to obtain an aerial image on a wafer. A resist model is applied to the aerial image to obtain a final resist image on the wafer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Jen Lai, Xin Zhou, Danping Peng
  • Patent number: 11133701
    Abstract: An apparatus for charging and mutual charging a combination of intelligent devices. The apparatus comprises a main device and an accessory device. The main device comprises a first control module and a first switch for switching on and off a first charging port. The accessory device comprises a second control module and a second switch for switching on and off a second charging port. The first control module is electrically connected to the second control module to realize mutual charging between intelligent devices. During outdoor use, one device when running out of power is automatically charged by another device until the combination of devices is completely out of power.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: September 28, 2021
    Assignee: HuiZhou TCL Mobile Communication Co., Ltd.
    Inventors: Chulong Sheng, Wentao Huang, Xiongcai Wu
  • Patent number: 11120189
    Abstract: A method of forming a mixed mode response from a single ended mode input includes modeling a first voltage controlled current source based on relative values of a vpositive input signal and a vnegative input signal and modeling a second voltage controlled current source based on relative values of the vpositive input signal and the vnegative input signal. A method of forming a single ended mode response from a mixed mode input modeling a first voltage controlled current source based on relative values of a vDIFFin input signal and a vCOMMin input signal and modeling a second voltage controlled current source based on relative values of the vDIFFin input signal and the vCOMMin input signal, the second voltage controlled being connected to ground through a second terminating impedance that is equal to the reference impedance (Z0).
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Zhaoqing Chen
  • Patent number: 11114885
    Abstract: A wireless charging system comprises (i) a transmitter structure comprising a first metallic core disposed in an opening of the transmitter structure and (ii) a receiver structure comprising a second metallic core disposed in an opening of the receiver structure. The transmitter structure is configured to carry one or more radio frequency (RF) signals to the first metallic core when the receiver structure is within a threshold distance from the transmitter structure. In addition, the receiver structure is configured to be excited by the one or more RF signals from the transmitter structure, whereby the one or more RF signals are transferred from the first metallic core to the second metallic core when the transmitter structure and the receiver structure are within the threshold distance from each other.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 7, 2021
    Assignee: Energous Corporation
    Inventors: Alister Hosseini, Michael A. Leabman
  • Patent number: 11108279
    Abstract: A method and an apparatus are provided for determining a cross connection during wireless charging. The method includes transmitting a first power to a plurality of wireless power receivers, based on first voltage setting information of a first wireless power receiver from among the plurality of wireless power receivers; determining to identify whether the wireless power transmitter is cross-connected with a second wireless power receiver from among the plurality of wireless power receivers; receiving second voltage setting information from the second wireless power receiver, while transmitting the first power to the plurality of wireless power receivers; transmitting a second power the plurality of wireless power receivers based on the second voltage setting information of the second wireless power receiver; and receiving measured voltage information from the second wireless power receiver, while transmitting the second power to the plurality of wireless power receivers.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: August 31, 2021
    Inventors: Kyung-Woo Lee, Hee-Won Jung
  • Patent number: 11100020
    Abstract: Novel tools and techniques in a telecommunication network are provided for implementing a data link layer control plane that may comply with the Ethernet standard and with sub-millisecond transmission control capabilities across multiple dis-similar technologies and bandwidth links. The framework provides a dynamic modular traffic control function insertion, removal, mapping function by having interpreter functions in the protocol agents that can map states and commands to sub-service chain functions that are configured per path and quality of service (QoS) flows. The control protocol provides high levels of resiliency and reliability by having a replicating function that transmits the same control protocol frames across multiple links simultaneously. The agents are multi-chassis capable and support hitless service impacts for administrative changes. Control plane messages may be encoded as a data plane frame and be transmitted at a high rate using the data plane.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 24, 2021
    Assignee: EOS Defense Systems USA, Inc.
    Inventors: Sunil Praful Shah, Ranjit Vadlamudi, Michael K. Bugenhagen, Aniruddha R. Karmarkar, Mark B. Saxelby, Abelino C. Valdez
  • Patent number: 11093680
    Abstract: The independent claims of this patent signify a concise description of embodiments. Roughly described, a design team prioritizes polygons of a circuit design layout. This information is then encoded into a layout database that is passed to the manufacturing team for correction further processing toward tape-out. The priorities may be used by an engineer to disposition errors found in the layout. For example, a failure may be waived. In another embodiment, the priorities are used during hotspot fixing, a process where failed features are corrected. In hotspot fixing, the priority can be used to make correction tradeoffs in favor of the highest priority features. Priorities are set during the correction to favor fidelity of the higher priority features over the lower priority features. Each embodiment reduces cost, and in some cases, improve final device performance. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: August 17, 2021
    Assignee: Synopsys, Inc.
    Inventors: Lawrence S. Melvin, III, Frank L. Ferschweiler
  • Patent number: 11093672
    Abstract: A method for implementing physical optimizations includes performing physical optimizations on a first reference version of a design, maintaining a computer-readable list of the physical optimizations, and during a subsequent compile for a second version of the design: identifying matching cells, nets, or both between the first reference version of the design and the second version of the design; and restoring at least a subset of the physical optimizations in the second version of the design by reading the computer-readable list of the physical optimizations and applying the subset to a computer-readable description of the second version of the design.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: August 17, 2021
    Assignee: Altera Corporation
    Inventors: Junaid Asim Khan, Gabriel Quan, Ketan Padalia, Scott James Brissenden, Ryan Fung
  • Patent number: 11079672
    Abstract: A method and a system of performing layout enhancement include: providing a first design layout comprising a plurality of cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; updating a second cell from remaining cells in the first design layout based on the data set to provide a second updated cell; and manufacturing a mask based on the first updated cell and the second updated cell in the first design layout.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Lin Chu, Hsin-Lun Tseng, Sheng-Wen Huang, Chih-Chung Huang, Chi-Ming Tsai
  • Patent number: 11080448
    Abstract: A method for formal deep bug hunting in a device under test (DUT) may include obtaining a selection of a start state for the DUT; obtaining a selection of one or a plurality of variables that are declared as random variables; for each of said one or a plurality of random variables, generating a sequence of random values in a generation order using a random number generator (RNG); and performing formal verification exploration of the DUT starting at the start state and consecutively assigning each of said one or a plurality of random variables a value from the sequence of values in the generation order.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: August 3, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yaron Schiller, Guy Wolfovitz, Habeeb Farah
  • Patent number: 11081898
    Abstract: A system for electrically de-bonding a battery from an electronic device includes an electro-adhesive layer within a coupling between the battery and the electronic device. When a current a of predetermined magnitude is directed through the electro-adhesive between a first electrode and a second electrode, the electro-adhesive initiates a chemical reaction that weakens a bond between the battery and the electronic device.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 3, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Gregory S. Yoder, Scott Douglas Bowers, Craig D. Owen
  • Patent number: 11062068
    Abstract: An electronic computer-aided design tool includes a design module and a printed electronics printer coupled to the design module. The design module determines one or more design specifications for an electronic device. The printed electronics printer produces one or more printed electronics prototypes of the electronic device based at least in part on at least on at least one of the design specifications. In some embodiments, the electronic computer-aided design tool includes a prototype testing unit that tests prototypes made by the printed electronics printer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: July 13, 2021
    Inventor: Hanan Potash
  • Patent number: 11056892
    Abstract: Aspects of the present disclosure are directed to a method and/or apparatus for use with battery cells having an actual voltage-sourcing level that is at or above a specified battery-output level. Switch circuitry is selectively activated for passing current, and a monitoring circuit is responsive to activation of the switching circuitry by distributing energy corresponding to an actual voltage-sourcing level of a particular one of the battery cells to a voltage node. A voltage-measurement circuit provides an indication of the actual voltage-sourcing level across the particular battery cell by ascertaining voltage differentials between the voltage node and respective voltage nodes of the battery cell, the ascertained voltage differentials being less than the specified battery-output level.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: July 6, 2021
    Assignee: NXP USA, Inc.
    Inventor: Guerric Panis
  • Patent number: 11050282
    Abstract: A power supply control method and device, a storage medium and an electronic device are provided. The method includes that: during charging, a battery is charged through a charging path of a charger, and power is supplied to an electronic device system through a power supplying path of the charger; a current voltage of the battery is detected in a charging process; whether the battery is completely charged or not is determined according to the current voltage of the battery; and the power supplying path of the charger and the charging path of the charger are turned off in response to determining that the battery is completely charged, and power is supplied to the electronic device system through the battery.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: June 29, 2021
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Qiang Zhang, Fanhong Kong, Fuchun Liao
  • Patent number: 11047919
    Abstract: An open wire detection system and method are provided. A semiconductor device includes a first diode having an anode terminal coupled to a first terminal and a cathode terminal coupled to a second terminal. The first and second terminals are configured for connection to a first battery cell terminal by way of a first conductive path and a second conductive path. A detect circuit is coupled to the first diode and is configured to provide a first open wire indication when a first voltage across the first diode exceeds a first threshold.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 29, 2021
    Assignee: NXP B.V.
    Inventors: Henricus Cornelis Johannes Büthker, Marijn Nicolaas van Dongen
  • Patent number: 11050288
    Abstract: In a storage-battery control system, an insulating communication unit couples a controller to a battery module constituting a storage battery unit that outputs a predetermined high voltage value. A power supply line is further provided for supplying electric power output from a controller DC/DC, i.e., a controller-side voltage converter for the controller, to the battery module, so that electric power is collectively supplied via the power supply line to a module CPU and a module-side insulating circuit both consuming electric power in the battery module. A secondary battery in the battery module supplies electric power to only a cell-voltage detector.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: June 29, 2021
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takahiro Kamikawa, Masayuki Kobayashi, Takayuki Mino
  • Patent number: 11036126
    Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 15, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chieh-Yu Lin, Dongbing Shao, Kehan Tian, Zheng Xu
  • Patent number: 11036146
    Abstract: A method including: obtaining information regarding a patterning error in a patterning process involving a patterning device; determining a nonlinearity over a period of time introduced by modifying the patterning error by a modification apparatus according to the patterning error information; and determining a patterning error offset for use with the modification apparatus based on the determined nonlinearity.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: June 15, 2021
    Assignee: ASML Netherlands B. V.
    Inventors: Richard Johannes Franciscus Van Haren, Everhardus Cornelis Mos, Peter Ten Berge, Peter Hanzen Wardenier, Erik Jensen, Hakki Ergün Cekli
  • Patent number: 11029594
    Abstract: A method including obtaining a selected component of optical aberration of or for a lithography apparatus, under a processing condition; computing an approximate of a cost function, based on the selected component; and producing an adjustment of the lithography apparatus or a patterning process that uses the lithography apparatus, based on the approximate of the cost function.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 8, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Steven George Hansen, Kateryna Stanislavovna Lyakhova, Paulus Jacobus Maria Van Adrichem