Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.

Abstract: A method for producing an optoelectronic semiconductor chip is disclosed. A semiconductor body has a pixel area, which has at least two different subpixel areas. An electrically conductive layer is applied to the radiation outlet surface of at least one subpixel area. The electrically conductive layer is designed to at least partially salify with a protic reaction partner. A conversion layer is deposited onto the electrically conductive layer by means of a electrophoresis process.

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device including a substrate, an oxide semiconductor layer, two source/drain regions, a high-k dielectric layer and a bottom oxide layer. The oxide semiconductor layer is disposed on a first insulating layer disposed on the substrate. The source/drain regions are disposed on the oxide semiconductor layer. The high-k dielectric layer covers the oxide semiconductor layer and the source structure and the drain regions. The bottom oxide layer is disposed between the high-k dielectric layer and the source/drain regions, wherein the bottom oxide layer covers the source/drain regions and the oxide semiconductor layer.

Abstract: An ESD protection structure comprising a first semiconductor region of a first doping type, a second semiconductor region of the first doping type, a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the first and second semiconductor regions of the first doping type, and a first contact region of the second doping type formed within a surface of the second semiconductor region. A thyristor structure is formed within the ESD protection structure comprising the first contact region of the second doping type, the second semiconductor region of the first doping type, the semiconductor structure of the second doping type, and the first semiconductor region of the first doping type. Wherein no contact region is formed within a surface of the semiconductor structure of the second doping type between the first and second semiconductor regions of the first doping type.

Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

Abstract: A method for manufacturing a semiconductor package including providing a first semiconductor package including a first package substrate and a first solder ball, the first package substrate having a first surface and a second surface opposite to the first surface, the first solder ball on the first surface, providing a second semiconductor package including a second package substrate and a second solder ball, the second package substrate having a third surface and a fourth surface opposite to the third surface, the second solder ball on the third surface, forming a depression in the first solder ball, applying flux to the first solder ball to fill the depression, aligning the first semiconductor package and the second semiconductor package with each other such that the second solder ball is inserted into the depression, and performing a reflow process to combine the first solder ball with the second solder ball may be provided.

Abstract: Methods for forming metal contacts having tungsten liner layers are provided herein. In some embodiments, a method of processing a substrate includes: exposing a substrate, within a first substrate process chamber, to a plasma formed from a first gas comprising a metal organic tungsten precursor gas or a fluorine-free tungsten halide precursor to deposit a tungsten liner layer, wherein the tungsten liner layer is deposited atop a dielectric layer and within a feature formed in a first surface of the dielectric layer of a substrate; transferring the substrate to a second substrate process chamber without exposing the substrate to atmosphere; and exposing the substrate to a second gas comprising a tungsten fluoride precursor to deposit a tungsten fill layer atop the tungsten liner layer.

Abstract: A method for forming patterns includes forming an etch target layer; etching the etch target layer to form a pre-pattern having a line forming portion and a plurality of pad portions; forming a plurality of spacers which extend across the pad portions and the line forming portion; forming, over the spacers, a blocking layer having an opening which blocks the pad portions and exposes the line forming portion; and etching the line forming portion by using the blocking layer and the spacers as a barrier, to form a plurality of line portions.

Abstract: A method for manufacturing a semiconductor device includes forming first and second lower structures including selection elements on first and second chip regions of a substrate, respectively, forming first and second mold layers on the first and second lower structures, respectively, forming first and second support layers on the first and second mold layers, respectively, patterning the first support layer and the first mold layer to form first holes exposing the first lower structure, forming first lower electrodes in the first holes, forming a support pattern including at least one opening by selectively patterning the first support layer while leaving the second support layer, and removing the first mold layer through the opening. A top surface of the support pattern is disposed at a substantially same level as a top surface of the second support layer.

Abstract: A method for manufacturing a PCRAM memory includes forming in a first dielectric layer arranged on a substrate, which includes bottom electrodes, a first rectilinear trench opening onto the set of electrodes; depositing a first active layer in the first trench, such that the first active layer is in electrical contact with the electrodes; covering the first active layer with a second dielectric layer; etching, in the second and second dielectric layers and the first active layer, additional rectilinear trenches oriented perpendicularly to the first trench, to obtain a group of memory devices each including a portion of the first active layer in electrical contact with one of the electrodes; filling the additional trenches with a sacrificial dielectric material; performing an anisotropic etching of the sacrificial material to expose a side surface of each portion of the first active layer; and covering the side surface with a second active layer.

Abstract: Disclosed are methods of forming different shapes in different regions of a specific layer. In the methods, a first mask layer and an etch process are used to form first shapes in a first region. Subsequently, a second mask layer and additional etch process(es) are used to form second shapes in a second region. However, before the second shapes are formed, a sacrificial layer of a degradable material is deposited onto the first mask layer and within openings in the specific layer surrounding the first shapes, thereby protecting the first shapes during formation of the second shapes. After the second shapes are formed, the material of the sacrificial layer is degraded (e.g., oxidized, volatilized, burned-off, etc.) so as to selectively remove that material from surfaces of the first mask layer and the specific layer without impacting the profiles of either the first shapes or the second shapes.

Abstract: A method of device processing. The method may include providing a cavity in a layer, directing energetic flux to a bottom surface of the cavity, performing an exposure of the cavity to a moisture-containing ambient, and introducing a fill material in the cavity using an atomic layer deposition (ALD) process, wherein the fill material is selectively deposited on the bottom surface of the cavity with respect to a sidewall of the cavity.

Abstract: A method for forming gate structures for a HV device and a MV device is provided. The method includes forming a HV oxide layer on the substrate, covering a first region predetermined for forming the HV device. Further in the method, a dielectric mask is formed on a central portion of the HV oxide layer. A thermal oxidation process is performed to form a MV oxide layer on the substrate at a second region predetermined for forming the MV device, wherein peripheral portions of the HV oxide layer not covered by the dielectric mask grow thicker. The dielectric mask is removed. A conductive layer is formed over the substrate. The conductive layer, the HV oxide layer, the MV oxide layer are patterned to form the gate structures.

Abstract: A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.

Abstract: The number of manufacturing steps is reduced to provide a semiconductor device with high productivity and low cost. A semiconductor device with low power consumption and high reliability is provided. A photolithography process for forming an island-shaped semiconductor layer is omitted, and a semiconductor device is manufactured through at least four photolithography processes: a step for forming a gate electrode (including a wiring or the like formed from the same layer), a step for forming a source electrode and a drain electrode (including a wiring or the like formed from the same layer), a step for forming a contact hole, and a step for forming a pixel electrode. In the step for forming the contact hole, a groove portion is formed, whereby formation of a parasitic transistor is prevented. The groove portion overlaps with the wiring with an insulating layer provided therebetween.

Abstract: In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer.

Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

Abstract: A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a first ILD, a cap covering the first ILD, the second metal line and a portion of the first metal line, a second ILD on the cap, and a via that electrically connects the first metal line to a third metal line, wherein the third metal line is above the first metal line and runs perpendicular to the first metal line, the via is fully aligned to the first metal line and the third metal line, and the via electrically connects the first metal line to the third metal line.